2.3.9. Register 6, Protection Region Base and Size Registers

These registers define the protection region base address and size. You can define eight programmable regions using these registers. The values are ignored when the protection unit is disabled, and on reset only the region enable bit for each region is reset to 0. All other bits are undefined. You must program at least one memory region before you enable the protection unit.

The instructions used to access the eight Protection Region Base and Size Registers are listed in Table 2.16.

Table 2.16. Accessing Protection Region Base and Size Registers

ARM instruction

Protection Region Base and Size Register

MCR/MRC p15, 0, Rd, c6, c7, 0

Memory region 7

MCR/MRC p15, 0, Rd, c6, c6, 0

Memory region 6

MCR/MRC p15, 0, Rd, c6, c5, 0

Memory region 5

MCR/MRC p15, 0, Rd, c6, c4, 0

Memory region 4

MCR/MRC p15, 0, Rd, c6, c3, 0

Memory region 3

MCR/MRC p15, 0, Rd, c6, c2, 0

Memory region 2

MCR/MRC p15, 0, Rd, c6, c1, 0

Memory region 1

MCR/MRC p15, 0, Rd, c6, c0, 0

Memory region 0

Each Protection Region Base and Size Register has the format shown in Table 2.17.

Table 2.17. Protection Region Base and Size Register format

Register bits

Function

[31:12]

Region base address

[5:1]

Region size

[0]

1 = Region enable

0 = Region disable

Reset to 0

You must align the region base to a region size boundary, where the region size is defined in its respective protection region register. The behavior is Unpredictable if this is not done.

Region sizes are encoded as shown in Table 2.18.

Table 2.18. Region size encoding  

Bit encodingRegion size

b00000 to b01010

Reserved (UNP)

b01011

4KB

b01100

8KB

b01101

16KB

b01110

32KB

b01111

64KB

b10000

128KB

b10001

256KB

b10010

512KB

b10011

1MB

b10100

2MB

b10101

4MB

b10110

8MB

b10111

16MB

b11000

32MB

b11001

64MB

b11010

128MB

b11011

256MB

b11100

512MB

b11101

1GB

b11110

2GB

b11111

4GB

Example base setting

An 8KB size region aligned to an 8KB boundary at 0x00002000 (covering the address range 0x00002000-0x00003FFF) is programmed as 0x00002019.

The following instruction is supported for backward compatibility with other ARM processors using a memory protection unit:

MRC p15, 0, Rd, c6, CRm, 1; returns protection region register

This instruction enables the protection region registers to be read.

You must not write to the protection region base and size registers with opcode_2 set to 1 because the behavior is Unpredictable.

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