To provide predictable code behavior in embedded systems, a mechanism is provided for locking code into the caches. For example, you can use this feature to hold high-priority interrupt routines where there is a hard real-time constraint, or to hold the coefficients of a DSP filter routine to reduce external bus traffic.

You can lock down a region of the instruction cache or data cache by executing a short software routine, taking note of these requirements:

You can carry out lockdown in the data cache using CP15 register 9. Instruction cache lockdown uses both CP15 registers 7 and 9.

As described in About cache architecture, the ARM946E-S instruction cache and data cache each comprise four segments. You can perform lockdown with a granularity of one segment. Lockdown starts at segment zero, and can continue until three of the four segments are locked.