When the data cache is enabled, it is searched when the processor performs a load or store. If the cache hits on a load, data is returned from the cache if the Cd bit is 1. If the cache read-misses, the Cd bit is examined. Table 3.2 shows the meaning of the values of the Cd bit.

Stores that hit in the cache update the cache line if the Cd bit is 1. Stores that miss the cache use the Cd and Bd bits to determine whether the write is buffered. A write miss is not loaded into the cache as a result of that miss.

Load and store multiples are broken up on 4KB boundaries (the minimum protection region size), enabling a protection check to be performed in case the Load Multiple (LDM) or Store Multiple (STM) crosses into a region with different protection properties.