3.3.5. Data cache clean and flush

The data cache has flexible cleaning and flushing utilities that enable the following operations:

You perform the cleaning and flushing operations using CP15 register 7, in a similar way to the instruction cache.

The format of Rd transferred to CP15 for all register 7 operations is shown in Figure 3.3.

Figure 3.3. Register 7, Rd format

The value of N depends on the cache size, as shown in Table 3.3.

Table 3.3. Calculating index addresses

Cache size

Value of N

4KB

9

8KB

10

16KB

11

32KB

12

64KB

13

128KB

14

256KB

15

512KB

16

1MB

17

The value of N is derived from the following equation:

Where the number of sets x the line length in bytes is 128.

It is usual to clean the cache before flushing it, so that external memory is updated with any dirty data. The following code segment shows how you can clean and flush the entire cache (assuming a 4KB data cache):

    MOV    r1, #0                        ; Initialize segment counter outer_loop
    MOV    r0, #0                        ; Initialize line counter inner_loop
    ORR    r2, r1, r0                    ; Generate segment and line address
    MCR    p15, 0, r2, c7, c14, 2        ; Clean and flush the line
    ADD    r0, r0, #0x20                 ; Increment to next line
    CMP    r0, #0x400                    ; Complete all entries in one segment?
    BNE    inner_loop                    ; If not branch back to inner_loop
    ADD    r1, r1, #0x40000000           ; Increment segment counter
    CMP    r1, #0x0                      ; Complete all segments
    BNE    outer_loop                    ; If not branch back to outer_loop
                                         ; End of routine
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