6.2.2. Transfer type

Table 6.1 shows the transfer types that can be generated by the ARM946E-S processor from the HTRANS[1:0] signal.

Table 6.1. AHB transfer types

Transfer typeHTRANS[1:0]Description

IDLE

b00

Indicates that no data transfer is required. The IDLE transfer is used when a bus master is granted the bus, but does not want to perform a data transfer. Slaves must always provide a zero wait state OKAY response to IDLE transfers and the transfer must be ignored by the slave.

BUSY

b01

The BUSY transfer enables bus masters to insert idle cycles in the middle of bursts of transfers. This transfer indicates that the bus master is continuing with a burst of transfers, but the next transfer cannot take place immediately. When a master uses the BUSY transfer the address and control signals must reflect the next transfer in the burst.

The transfer must be ignored by the slave. Slaves must always provide a zero wait state OKAY response, in the same way that they respond to IDLE transfers.

Examples of where the ARM946E-S uses BUSY cycles are:

  • during debug and coprocessor operations to uncachable areas of memory

  • LDM accesses to uncachable areas of memory depending on the start address of the burst.

NONSEQ

b10

Indicates the first transfer of a burst or a single transfer. The address and control signals are unrelated to the previous transfer. Single transfers on the bus are treated as bursts of one and therefore the transfer type is NONSEQUENTIAL.

SEQ

b11

The remaining transfers in a burst are SEQUENTIAL and the address is related to the previous transfer. The control information is identical to the previous transfer. The address is equal to the address of the previous transfer plus the size (in bytes).

Note

BUSY transfers are inserted between certain sequences of NONSEQ and SEQ transfers. Examples of transfers that can cause BUSY transfers include multiple data reads during debug and coprocessor operations to uncachable areas of memory. LDM accesses to uncachable areas of memory might also cause BUSY transfers depending on the start address of the burst.

System designers must ensure that any AHB peripherals can handle BUSY transfers as defined in the AMBA Specification.

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