7.2.3. Coprocessor handshake states

The handshake signals encode one of four states:

ABSENT

If there is no coprocessor attached that can execute the coprocessor instruction, the handshake signals indicate the ABSENT state. In this case, the ARM9E-S core takes the undefined instruction trap.

WAIT

If there is a coprocessor attached that can handle the instruction, but not immediately, the coprocessor handshake signals are driven to indicate that the ARM9E-S processor core must stall until the coprocessor can catch up. This is known as the busy-wait condition. In this case, the ARM9E-S processor core loops in an IDLE state waiting for CHSEX[1:0] to be driven to another state, or for an interrupt to occur. If CHSEX[1:0] changes to ABSENT, the undefined instruction trap is taken. If CHSEX[1:0] changes to GO or LAST, the instruction proceeds as described here. If an interrupt occurs, the ARM9E-S processor is forced out of the busy-wait state. This is indicated to the coprocessor by the CPPASS signal going LOW. The instruction is restarted later and so the coprocessor must not commit to the instruction (it must not change any coprocessor state) until CPPASS is asserted HIGH, when the handshake signals indicate the GO or LAST condition.

GO

The GO state indicates that the coprocessor can execute the instruction immediately, and that it requires at least another cycle of execution. Both the ARM9E-S processor core and the coprocessor must also consider the state of the CPPASS signal before actually committing to the instruction. For an LDC/STC instruction, the coprocessor instruction drives the handshake signals with GO when two or more words still have to be transferred. When only one more word is to be transferred, the coprocessor drives the handshake signals with LAST. During the Execute stage, the ARM9E-S processor core outputs the address for the LDC/STC instruction. Also in this cycle, DnMREQ is driven LOW, indicating to the ARM946E-S memory system that a memory access is required at the data end of the device. The timing for the data on CPDOUT and CPDIN is shown in Figure 7.6.

LAST

An LDC or STC instruction can be used for more than one item of data. If this is the case, possibly after busy waiting, the coprocessor drives the coprocessor handshake signals with a number of GO states, and in the penultimate cycle LAST (LAST indicating that the next transfer is the final one). If there is only one transfer, the sequence is [WAIT,[WAIT,...]],LAST. LAST is also usually driven for CDP instructions.

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