9.5.2. Debug access to the caches, Step 2

Reading individual entries using the CP15 scan chain can be useful where an entry has been marked as dirty, because this indicates that there is an inconsistency between the cache contents and main memory.

For the data cache, the debugger can execute system speed accesses that hit in the cache and, therefore, return the cache contents. Writes to the data cache from the processor core by this method result in the dirty bits being set for write-back regions, and main memory is updated for write-through regions.

If the CP15 scan chain is used for updating the data cache, only the cache contents are updated. Writes are not made to main memory. For this method you must first program the Index/Set Register with the required cache index, set, and word values. Figure 9.6 shows the format of the Cache Index Register.

Figure 9.6. Cache Index Register format


Although 27 bits are specified for the TAG address, only those bits required for the TAG implemented are used.

The Cache Index Register is also used for writing to the instruction cache. This is useful for setting software breakpoints within code already in the cache. This means that you do not have to flush the cache and reload the entry.


There is no mechanism for detecting that the instruction cache has been updated in this way. The debugger must restore the original cache contents after executing the breakpoint.

Copyright © 2001-2003, 2007 ARM Limited. All rights reserved.ARM DDI 0201D