ARM946E-S ™ TechnicalReference Manual

Revision: r1p1

Home

ARM946E-S ™ TechnicalReference Manual

Revision: r1p1

Copyright © 2001-2003, 2007 ARM Limited. All rights reserved.

Proprietary notices

Table of Contents

About this document

Product revision status
Intended audience
Using this manual
Conventions
Further reading

Feedback on the ARM946E-S processor
Feedback on this manual

1. Introduction

1.1. About the ARM946E-S processor
1.2. ARM946E-S block diagram
1.3. Differences between processor versions

2. Programmer’s Model

2.1. About the ARM946E-S programmer’s model

2.2. About the ARM9E-S programmer’s model

2.2.1. Data Abort model

2.3. CP15 register map summary

2.3.1. Accessing CP15 registers
2.3.2. Register 0, ID Code Register
2.3.3. Register 0, Cache Type Register
2.3.4. Register 0, Tightly-coupled MemorySize Register
2.3.5. Register 1, Control Register
2.3.6. Register 2, Cache Configuration Registers
2.3.7. Register 3, Write Buffer Control Register
2.3.8. Register 5, Access Permission Registers
2.3.9. Register 6, Protection Region Baseand Size Registers
2.3.10. Register 7, Cache Operations Register
2.3.11. Register 9, Cache Lockdown Registers
2.3.12. Register 9, Tightly-coupled MemoryRegion Registers
2.3.13. Register 13, Trace Process IdentifierRegister
2.3.14. Register 15, BIST Control Registers
2.3.15. Register 15, Test State Register
2.3.16. Register 15, Cache Debug Index Register
2.3.17. Register 15, Trace Control Register

3.1. About cache architecture

3.2. Instruction cache

3.2.1. Enabling and disabling the instruction cache
3.2.2. Instruction cache operation
3.2.3. Instruction cache validity

3.3. Data cache

3.3.1. Enabling and disabling the data cache
3.3.2. Operation of the Bd and Cd bits
3.3.3. Data cache operation
3.3.4. Data cache validity
3.3.5. Data cache clean and flush

3.4. Cache lockdown

3.4.1. Locking down the caches

4. Protection Unit

4.1. About the protection unit

4.1.1. Enabling the protection unit

4.2. Memory regions

4.2.1. Region base address
4.2.2. Region size
4.2.3. Partition attributes

4.3. Overlapping regions

4.3.1. Background regions

5. Tightly-Coupled Memory Interface

5.1. ARM946E-S TCM interface description

5.2. Using CP15 Control Register

5.2.1. Enabling the Instruction TCM
5.2.2. Disabling the Instruction TCM
5.2.3. Defining the physical and visible size of the InstructionTCM
5.2.4. Initializing the Instruction TCM
5.2.5. Enabling the Data TCM
5.2.6. Disabling the Data TCM
5.2.7. Defining the physical and visible size of the DataTCM
5.2.8. Initializing the Data TCM

5.3. Enabling the Instruction TCM duringsoft reset

5.4. Data TCM accesses

5.5. Instruction TCM accesses

5.5.1. Instruction accesses to Instruction TCM
5.5.2. Data accesses to Instruction TCM
5.5.3. Stall cycles for Instruction TCM accesses

6. Bus Interface Unit and Write Buffer

6.1. About the BIU and write buffer

6.2. AHB bus master interface

6.2.1. About AHB
6.2.2. Transfer type
6.2.3. Burst sizes
6.2.4. Linefetch transfers
6.2.5. Back to back linefetches
6.2.6. Uncached transfers
6.2.7. Burst accesses
6.2.8. Bursts crossing 1KB boundary
6.2.9. Uncached LDC operations

6.3. Noncached Thumb instruction fetches

6.4. AHB clocking

6.4.1. CLK to HCLK skew

6.5. The write buffer

6.5.1. Write buffer operation
6.5.2. Enabling and disabling the write buffer
6.5.3. Self-modifying code

7. Coprocessor Interface

7.1. About the coprocessor interface

7.2. Coprocessor interface signals

7.2.1. Synchronizing the external coprocessor pipeline
7.2.2. External coprocessor clocking
7.2.3. Coprocessor handshake states
7.2.4. Coprocessor handshake encoding
7.2.5. Multiple external coprocessors

7.3. LDC/STC

7.4. MCR/MRC

7.5. Interlocked MCR

7.7. Privileged instructions

7.8. Busy-waiting and interrupts

8. ETM Interface

8.1. About the ETM interface

8.2. Enabling the ETM interface

8.3. ARM946E-S trace support features

8.3.1. ETMFIFOFULL
8.3.2. Register 15, Trace Control Register
8.3.3. Register 13, Trace Process IdentifierRegister

9. Debug Support

9.1. About the debug interface

9.1.1. Halt mode
9.1.2. Monitor mode
9.1.3. Debug clocks

9.2. Debug systems

9.2.1. The debug host
9.2.2. The protocol converter
9.2.3. ARM946E-S debug target

9.3. The JTAG state machine

9.3.1. Reset
9.3.2. Instruction Register
9.3.3. Public instructions

9.4. Scan chains

9.4.1. Scan chain 1
9.4.2. Scan chain 2
9.4.3. Scan chain 15
9.4.4. Scan Chain Debug Status Register

9.5. Debug access to the caches

9.5.1. Debug access to the caches, Step 1
9.5.2. Debug access to the caches, Step 2

9.6. Debug interface signals

9.6.1. Entry into debug state on breakpoint
9.6.2. Breakpoints and exceptions
9.6.3. Watchpoints
9.6.4. Watchpoints and exceptions
9.6.5. Debug request
9.6.6. Actions of the ARM9E-S in debug state

9.7. Determining the core and system state

9.8. Overview of EmbeddedICE-RT

9.9. Disabling EmbeddedICE-RT

9.10. The debug communication channel

9.10.1. Debug Communication Channel Registers
9.10.2. Debug Communication Channel Status Register
9.10.3. Communications using the communication channel

9.11. Monitor mode debugging

9.11.1. Debug in depth

10. Test Support

10.1. About the ARM946E-S processor testmethodology

10.2. Scan insertion and ATPG

10.2.1. ARM946E-S INTEST wrapper

10.3. BIST of memory arrays

10.3.1. BIST algorithm
10.3.2. BIST Control Register
10.3.3. BIST Address and General Registers
10.3.4. Pause modes
10.3.5. Running a test

A. AC Parameters

A.1. Timing diagrams

B. Signal Descriptions

B.1. Signal properties and requirements
B.2. Clock interface signals
B.3. TCM interface signals
B.4. AHB signals
B.5. Coprocessor interface signals
B.6. Debug signals
B.7. JTAG signals
B.8. Miscellaneous signals
B.9. ETM interface signals
B.10. INTEST wrapper signals

List of Figures

1. Key to timing diagram conventions
1.1. ARM946E-S processor block diagram
2.1. CP15 MRC and MCR bit pattern
2.2. Register 7, Index and segment format
2.3. Instruction cache address format
2.4. Process ID format
2.5. Register 15, Index and segment format
2.6. Data format TAG read/write operations
3.1. Example 8KB cache
3.2. Access address for a 4KB cache
3.3. Register 7, Rd format
4.1. Protection unit
4.2. Overlapping memory regions
5.1. TCM read cycle
5.2. Data write followed by data readof Data TCM
5.3. Simultaneous instruction fetch anddata read of Instruction TCM
5.4. Data write followed by data readof Instruction TCM
5.5. Data write followed by instructionfetch of Instruction TCM
5.6. Data read followed by instructionfetch
5.7. Simultaneous instruction fetch anddata write
5.8. Data write followed by simultaneousinstruction fetch and data read
6.1. Linefetch transfer
6.2. Back-to-back line fetches
6.3. Nonsequential uncached accesses
6.4. Data burst followed by instructionfetch
6.5. Crossing a 1KB boundary
6.6. Uncached LDC sequence
6.7. AHB clock relationships
6.8. ARM946E-S CLK to AHB HCLK sampling
7.1. Pipeline stages
7.2. Connecting multiple coprocessors
7.3. Example handshake logic blocks
7.4. Driving the coprocessors data busesto logic 0
7.5. Multiplexing the coprocessors databuses
7.6. LDC/STC cycle timing
7.7. MCR/MRC transfer timing with busy-wait
7.8. Interlocked MCR/MRC timing with busy-wait
7.9. Late canceled CDP
7.10. Privileged instructions
7.11. Busy-waiting and interrupts
8.1. ARM946E-S ETM interface
9.1. Clock synchronization
9.2. Typical debug system
9.3. ARM9E-S block diagram
9.4. TAP controller state transitions
9.5. TAG address format
9.6. Cache Index Register format
9.7. Breakpoint timing
9.8. Watchpoint entry with data processinginstruction
9.9. Watchpoint entry with branch
9.10. The ARM9E-S, TAP controller, andEmbeddedICE-RT
9.11. Debug Communication Channel StatusRegister
10.1. Test flow for BIST
A.1. Clock, reset, and AHB enable timing
A.2. AHB bus request and grant relatedtiming
A.3. AHB bus master timing
A.4. Coprocessor interface timing
A.5. Debug interface timing
A.6. JTAG interface timing
A.7. DBGSDOUT to DBGTDO timing
A.8. Exception and configuration timing
A.9. TCM interface timing
A.10. ETM interface timing

List of Tables

1.1. Location of block descriptions
2.1. CP15 register map
2.2. CP15 terms and abbreviations
2.3. Register 0, ID code
2.4. Cache Type Register format
2.5. Cache size encoding
2.6. Cache associativity encoding
2.7. Tightly-coupled Memory Size Register
2.8. Memory size field
2.9. Register 1, Control Register
2.10. Programming instruction and data cachable bits
2.11. Programming data bufferable bits
2.12. Programming instruction and data access permission bits (extended)
2.13. Access permission encoding (extended)
2.14. Instruction and data access permission bits (standard)
2.15. Access permission encoding (standard)
2.16. Accessing Protection Region Base and Size Registers
2.17. Protection Region Base and Size Register format
2.18. Region size encoding
2.19. Cache operations
2.20. Index fields for supported cache sizes
2.21. Lockdown Register format
2.22. TCM Region Register format
2.23. TCM area size encoding
2.24. Register 15, BIST instructions
2.25. Register 15, implementation-specific BIST instructions
2.26. BIST Control Register bit definitions
2.27. BIST size encodings examples
2.28. Test State Register bit assignments
2.29. Additional operations
2.30. Index fields for supported cache sizes
2.31. Trace Control Register
2.32. Trace Control Register bit assignments
3.1. TAG and index fields for supported cache sizes
3.2. Meaning of Cd bit values
3.3. Calculating index addresses
4.1. Protection Register format
4.2. Region size encoding
6.1. AHB transfer types
6.2. Supported burst types
6.3. Data write modes
7.1. Coprocessor interface signals
7.2. Handshake encoding
9.1. Public instructions
9.2. ARM946E-S scan chain allocations
9.3. Scan chain 1 bits
9.4. Scan chain 2 bits
9.5. Scan chain 15 bits
9.6. Mapping of scan chain 15 address field to CP15 registers
9.7. Status bit mapping of scan chain 15 address field to CP15registers
9.8. Correlation between status bits and cache operations
9.9. Coprocessor 14 register map
10.1. Instruction BIST Address and General Registers
10.2. Data BIST Address and General Registers
A.1. Timing parameter definitions for clock, reset, and AHB enable
A.2. Parameter definitions for AHB bus request and grant timing
A.3. Parameter definitions for AHB bus master timing
A.4. Parameter definitions for coprocessor interface timing
A.5. Parameter definitions for debug interface timing
A.6. Parameter definitions for JTAG interface timing
A.7. Parameter definitions for DBGSDOUT to DBGTDO timing
A.8. Parameter definitions for exception and configuration timing
A.9. Parameter definitions for TCM interface timing
A.10. Parameter definitions for ETM interface timing
B.1. Clock interface signals
B.2. TCM interface signals
B.3. AHB signals
B.4. Coprocessor interface signals
B.5. Debug signals
B.6. JTAG signals
B.7. Miscellaneous signals
B.8. ETM interface signals

Proprietary Notice

Words and logos marked with ^® or ™ are registered trademarks or trademarksof ARM Limited in the EU and other countries, except as otherwisestated below in this proprietary notice. Other brands and names mentionedherein may be the trademarks of their respective owners.

Neither the whole nor any part of the information containedin, or the product described in, this document may be adapted orreproduced in any material form except with the prior written permissionof the copyright holder.

The product described in this document is subject to continuousdevelopments and improvements. All particulars of the product andits use contained in this document are given by ARM in good faith.However, all warranties implied or expressed, including but notlimited to implied warranties of merchantability, or fitness forpurpose, are excluded.

This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.

Figure 9.4 reprintedwith permission from IEEE Std. 1149.1-2001, IEEE Standard Test Access Portand Boundary-Scan Architecture by IEEE Std. The IEEE disclaims anyresponsibility or liability resulting from the placement and usein the described manner.

ConfidentialityStatus

This document is Non-Confidential. The right to use, copyand disclose this document may be subject to license restrictionsin accordance with the terms of the agreement entered into by ARMand the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision A	16February 2001	First release
Revision B	17May 2002	Second release
Revision C	15May 2003	Third release
Revision D	17April 2007	Various defects corrected

Copyright © 2001-2003, 2007 ARM Limited. All rights reserved.	ARM DDI 0201D
Non-Confidential
PDF version

Home