There are two possible configurations for a system that uses boot ROM:

For a system with internal ROM, the AHB Decoder handles selecting this device after reset to enable the processor to start executing from address 0x00000000. For a system with external ROM, the external memory controller must ensure that this device is available at address 0x00000000 no matter which chip select it is connected to.

In a system with internal RAM and external ROM, the most likely memory map configuration is to have the internal RAM at address 0x00000000. Because this RAM is likely to be quite small, it is useful to overlap the normally larger external RAM with this internal RAM, so the external RAM is located on bank zero and also at address 0x00000000. This enables an easy flow from internal RAM to external RAM, and makes it possible for the software to continue accessing the RAM without having to write to a completely different location if it exceeds the size of the internal RAM.

To accommodate this overlap of internal and external RAMs, the external boot ROM must be on a bank other than bank zero. For the Primecell SMC this boot ROM is available on bank seven.

The SMC therefore provides a REMAP input that is used to control the shadowing of the SMCS[7] memory area onto the SMCS[0] memory area after reset (REMAP = 0). This makes the memory at SMCS[0] unavailable until the system sets the REMAP input. When the REMAP input has been set HIGH (REMAP = 1), the SMCS[7] memory area is only available at SMCS[7], and the SMCS[0] memory area is available for normal use.

Chip selects SMCS[1] to SMCS[6] are unaffected by the REMAP input and are always available for access.