PrimeCell ™ Static MemoryController (PL092) Technical Reference Manual


Table of Contents

About this document
Product revision status
Intended audience
Using this manual
Further reading
Feedback on the ARM PrimeCell SMC
Feedback on this document
1. Introduction
1.1. About the SMC
1.1.1. Features of the PrimeCell SMC
1.1.2. Programmable parameters
1.2. Example of a typical system
1.3. Input and output connections
1.4. Synchronous AHB memory controller
1.5. Additional asynchronous memory controller
1.6. Product revisions
1.6.1. Section 2.8.1 SMWAIT assertion timing
2. Functional Overview
2.1. ARM PrimeCell SMC overview
2.2. SMC core
2.2.1. AMBA AHB interface
2.2.2. Transfer control
2.2.3. External bus interface
2.3. Memory bank selection
2.4. Memory bank configuration
2.4.1. Access sequencing and memory width
2.4.2. Wait state generation
2.4.3. Write protection
2.5. Static memory readcontrol
2.5.1. Output enable programmable delay
2.5.2. ROM, SRAM, and flash
2.5.3. Burst ROM
2.5.4. Burst flash
2.6. Static memory writecontrol
2.6.1. Write enable programmable delay
2.6.2. SRAM
2.6.3. Flash memory
2.7. Bus turnaround
2.8. External wait control
2.8.1. SMWAIT assertion timing
2.8.2. SMWAIT deassertion timing
2.8.3. SMWAIT timing diagrams
2.9. Byte lane control
2.9.1. Memory banks constructed from 8-bit or non byte-partitionedmemory devices
2.9.2. Memory banks constructed from 16 or 32-bit memorydevices
2.9.3. Elimination of floating bytes on the external interface
2.9.4. Byte lane control and data bus steering for littleand big-endian configurations
2.10. Memory shadowing
2.10.1. Booting from ROM after reset
2.10.2. External bank SMCS7 size configuration
2.11. Test interface controller operation
2.11.1. Function and operation of module
2.11.2. Test vector types
2.11.3. Control vectors
2.11.4. Test vector sequences
2.12. Data bus interface operation
2.13. Using the SMC with an external busmultiplexor or SDRAM controller
3. Programmer’s Model
3.1. About the programmer’s model
3.2. Summary of registers
3.3. Register descriptions
3.3.1. Bank Idle Cycle Control Registers0-7
3.3.2. Bank Wait State 1 ControlRegisters 0-7
3.3.3. Bank Wait State 2 ControlRegisters 0-7
3.3.4. Bank Output EnableAssertion Delay Control Registers 0-7
3.3.5. Bank Write EnableAssertion Delay Control Registers 0-7
3.3.6. Bank Control Registers 0-7
3.3.7. Bank Status Registers0-7
3.3.8. External Wait Status Register
3.3.9. Peripheral Identification Registers0-3
3.3.10. PrimeCell Identification Registers0-3
4. Programmer’s Model for Test
4.1. Scan testing
A. Signal Descriptions
A.1. AMBA AHB interface signals
A.2. AMBA AHB slave interface signals
A.3. AMBA AHB master interface signals
A.4. Internal signals
A.5. Input/output pad signals

List of Figures

1. Key to timing diagram conventions
1.1. Typical AMBA AHB-based microcontrollersystem
1.2. PrimeCell SMC input and output connections
1.3. AMBA AHB-based microcontroller systemwith SMC and SDRAM controller
1.4. Signal connections for additionalasynchronous memory controller
2.1. PrimeCell SMC block diagram
2.2. SMC core block diagram
2.3. External memory zero wait state read
2.4. External memory two wait state read
2.5. External memory two-output enabledelay and two wait state read
2.6. External memory zero wait state read,bus not granted
2.7. External memory three zero wait stateread
2.8. External memory zero wait fixed-lengthread
2.9. External memory two wait states fixed-lengthburst read
2.10. External burst ROM WST1 = 2, WST2= 1, fixed length burst read
2.11. External memory 32-bit burst readfrom 8-bit memory
2.12. External memory zero wait state write
2.13. External memory two wait state write
2.14. External memory two write enabledelay and two wait state write
2.15. External memory zero wait state write,bus not granted
2.16. External memory zero wait state write,bus not granted, external synchronous bus multiplexor
2.17. External memory two zero wait writes
2.18. Read followed by write (both zerowait) with no turnaround
2.19. Write followed by read (both zerowait) with no turnaround
2.20. Read followed by two writes (allzero wait state) with two turnaround cycles
2.21. External wait timed read transfer
2.22. External wait timed write transfer
2.23. External wait timed read transferwith external abort
2.24. Memory banks constructed from 8-bitmemory
2.25. Memory banks constructed from 16-bitmemory
2.26. Memory banks constructed from 32-bitmemory
2.27. Typical memory connection diagram
2.28. Test start sequence
2.29. Write test vectors
2.30. Read test vectors
2.31. Control vector
2.32. Read vector followed by a write vector
2.33. Example of bus interface timing
3.1. SMBIDCYRx Register bit assignments
3.2. SMBWST1Rx Register bit assignments
3.3. SMBWST2Rx Register bit assignments
3.4. SMBWSTOENRx Register bit assignments
3.5. SMBWSTWENRx Register bit assignments
3.6. SMBCRx Register bit assignments
3.7. SMBSRx Register bit assignments
3.8. SMBEWS Register bit assignments
3.9. SMCPeriphID Register bit assignments
3.10. SMCPCellID Register bit assignments

List of Tables

2.1. Static memory bank select coding
2.2. HADDR[31:0] address mapping
2.3. SMDATAOUT controlled by nSMDATAEN
2.4. Little-endian read, 8-bit external bus
2.5. Little-endian read, 16-bit external bus
2.6. Little-endian read, 32-bit external bus
2.7. Little-endian write, 8-bit external bus
2.8. Little-endian write, 16-bit external bus
2.9. Little-endian write, 32-bit external bus
2.10. Big-endian read, 8-bit external bus
2.11. Big-endian read, 16-bit external bus
2.12. Big-endian read, 32-bit external bus
2.13. Big-endian write, 8-bit external bus
2.14. Big-endian write, 16-bit external bus
2.15. Big-endian write, 32-bit external bus
2.16. External size configuration values for bank seven
2.17. Test control signals during normal operation
2.18. Test control signals during test operation
2.19. Control vector bit definitions
3.1. PrimeCell SMC read/write register summary
3.2. SMBIDCYRx Register bit assignments
3.3. SMBWST1Rx Register bit assignments
3.4. SMBWST2Rx Register bit assignments
3.5. SMBWSTOENRx Register bit assignments
3.6. SMBWSTWENRx Register bit assignments
3.7. PrimeCell SMC reset default memory width
3.8. SMBCRx Register bit assignments
3.9. SMBSRx Register bit assignments
3.10. SMBEWS Register bit assignments
3.11. SMCPeriphID Register options
3.12. SMCPeriphID0 Register bit assignments
3.13. SMCPeriphID1 Register bit assignments
3.14. SMCPeriphID2 Register bit assignments
3.15. SMCPeriphID3 Register bit assignments
3.16. SMCPCellID0 Register bit assignments
3.17. SMCPCellID1 Register bit assignments
3.18. SMCPCellID2 Register bit assignments
3.19. SMCPCellID3 Register bit assignments
A.1. Common AMBA AHB signals
A.2. AMBA AHB slave interface signals
A.3. AMBA AHB master interface signals
A.4. Internal signal descriptions
A.5. Input/output pad signals


Words and logos marked with ® or ™ are registered trademarks or trademarksof ARM Limited in the EU and other countries, except as otherwisestated below in this proprietary notice. Other brands and names mentionedherein may be the trademarks of their respective owners.

Neither the whole nor any part of the information containedin, or the product described in, this document may be adapted orreproduced in any material form except with the prior written permissionof the copyright holder.

The product described in this document is subject to continuousdevelopments and improvements. All particulars of the product andits use contained in this document are given by ARM Limited in goodfaith. However, all warranties implied or expressed, including butnot limited to implied warranties of merchantability, or fitnessfor purpose, are excluded.

This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.


This document is Non-Confidential. The right to use, copyand disclose this document may be subject to license restrictionsin accordance with the terms of the agreement entered into by ARMand the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision A April2001 First release
Revision B June2001 Signal changes to F1-3, Page 2-58, A-7, A-8
Revision C July2002 Incorporation of errata
Revision D January2003 Incorporation of errata
Revision E June2003 Additional signal incorporated, revision r1p3
Revision F December2003 Editorial update, register diagrams added,errata sheet incorporated, new Hardware Preface included, indexupdated
Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI 0203F