The clock gating signals are ETM10DFTGCKEN and ETM10DFTWCKEN. These signals enable the gating of:

While the clock gating signals are enabled, GCLK and ETM10WCLK are enabled.

The ETM10 patterns are created with GCLK and TCK driven separately. These two clock domains are not delay-matched, and the ETM10 scan patterns do not allow these clocks to toggle simultaneously during a capture cycle. The ETM10 wrapper clock (ETM10WCLK) is 180 degrees out of phase with GCLK during production scan mode, as shown in Figure 4.4. This prevents hold-timing issues, because GCLK and ETM10WCLK are not perfectly delay matched within the ETM10.

ETM10WCLK can be created by inverting GCLK, but the timing from the package pins to the ports of these two signals on the ETM10 must be closely delay-matched.