ETM10 ™ Technical ReferenceManual

Revision: r0p0


Table of Contents

Preface
About this manual
Product revision status
Intended audience
Using this manual
Conventions
Further reading
Feedback
Feedback on the product
Feedback on this manual
1. Introduction
1.1. About the ETM10
1.2. Supported standard configurations
2. Accessing the ETM10 Registers
2.1. The JTAG interface
2.2. ETM10 registers
3. Integrating the ETM10
3.1. About integrating the ETM10
3.1.1. ETM10 to ARM10 connection guide
3.2. ARM1020E trace interface
3.2.1. ETM10 datapath inputs
3.2.2. ETM10 control inputs
3.3. System control signals
3.3.1. Debug
3.3.2. Using the PWRDOWN signal
3.3.3. The FIFOFULL stall signal
3.3.4. The SYSOPT bus
3.4. Clocks and resets
3.4.1. GCLK
3.4.2. TCK
3.4.3. NRESET
3.4.4. NTRST
3.5. TAP interface wiring
3.5.1. Multiprocessor TAP structure
3.6. Trace port interfacing
3.6.1. Trace port logic
3.6.2. Single-processor tracing
3.6.3. Dual-processor tracing
3.6.4. PCB design guidelines
3.7. Modes of operation of the trace port
3.7.1. Normal trace port signals
3.7.2. Demultiplexed trace port signals
3.7.3. Operation with asynchronous TCK
4. Design for Test
4.1. About DFT
4.1.1. DFT modes
4.1.2. Scan chains
4.1.3. Clock signals
4.1.4. Asynchronous signals
4.2. Scan chain configurations
4.3. ETM10 test wrapper
4.3.1. Dedicated input wrapper cells
4.3.2. Dedicated output wrapper cells
4.3.3. Reset-dedicated wrapper cell
4.4. Test modes and ports
4.4.1. Selecting a test mode
4.4.2. Internal test mode
4.4.3. External test mode example
4.4.4. Serial core test mode
4.4.5. Functional mode
4.5. Clocks and gating
4.5.1. Clocking in serial core test mode
5. Implementation-defined Behavior
5.1. ETM architecture version
5.1.1. ETM ID register
5.2. Precise TraceEnable events
5.3. Parallel instruction execution
5.4. Independent load/store unit
5.5. The FIFOFULL level register
5.6. Context ID tracing
6. Tracing Dynamically-loaded Images
6.1. About tracing dynamically-loaded code
6.2. Software support for context ID
6.3. Hardware support for context ID
7. Physical Trace Port Signal Guidelines
7.1. About trace port signal quality
7.2. ASIC pad selection, placement, andpackage type
7.3. PCB design guidelines
7.3.1. Dedicated trace port
7.3.2. Shared trace port
7.4. EMI compliance
7.5. Further references
A. Signal Descriptions
A.1. Functional signals
A.2. DFT signals
Glossary

ProprietaryNotice

Words and logos marked with ® or ™ are registered trademarks or trademarksof ARM Limited in the EU and other countries, except as otherwisestated below in this proprietary notice. Other brands and names mentionedherein may be the trademarks of their respective owners.

Neither the whole nor any part of the information containedin, or the product described in, this document may be adapted orreproduced in any material form except with the prior written permissionof the copyright holder.

The product described in this document is subject to continuousdevelopments and improvements. All particulars of the product andits use contained in this document are given by ARM in good faith.However, all warranties implied or expressed, including but notlimited to implied warranties of merchantability, or fitness forpurpose, are excluded.

This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.

ConfidentialityStatus

This document is Non-Confidential. The right to use, copyand disclose this document may be subject to license restrictionsin accordance with the terms of the agreement entered into by ARMand the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision A 25July 2001 ETM10 (Rev 0) release.
Revision B 28Nov 2003 Second release r0p0. Updated to includeerrata fixes.
Copyright © 2001, 2003 ARM Limited. All rights reserved. ARM DDI 0206B
Non-Confidential