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The AC timing diagrams provided in this section are as follows.
Each diagram is provided with a table that describes the timing parameters. In the tables:
the letter f at the end of a signal name indicates the falling edge
the letter r at the end of a signal name indicates the rising edge.
In Figure 7.1, nWAIT, APE, ALE, and ABE are all HIGH during the cycle shown. Tcdel is the delay, on either edge (whichever is greater), from the edge of MCLK to ECLK.
The timing parameters used in Figure 7.1 are listed in Table 7.1.
Table 7.1. General timing parameters
| Symbol | Parameter | Parameter type |
|---|---|---|
| Taddr | MCLKr to address valid | Maximum |
| Tah | Address hold time from MCLKr | Minimum |
| Tbld | MCLKr to MAS[1:0] and LOCK | Maximum |
| Tblh | MAS[1:0] and LOCK hold from MCLKr | Minimum |
| Tcdel | MCLK to ECLK delay | Maximum |
| Texd | MCLKf to nEXEC and INSTRVALID valid | Maximum |
| Texh | nEXEC and INSTRVALID hold time from MCLKf | Minimum |
| Tmdd | MCLKr to nTRANS, nM[4:0], and TBIT valid | Maximum |
| Tmdh | nTRANS and nM[4:0] hold time from MCLKr | Minimum |
| Tmsd | MCLKf to nMREQ and SEQ valid | Maximum |
| Tmsh | nMREQ and SEQ hold time from MCLKf | Minimum |
| Topcd | MCLKr to nOPC valid | Maximum |
| Topch | nOPC hold time from MCLKr | Minimum |
| Trwd | MCLKr to nRW valid | Maximum |
| Trwh | nRW hold time from MCLKr | Minimum |
The timing parameters used in Figure 7.2 are listed in Table 7.2.
Table 7.2. ABE address control timing parameters
| Symbol | Parameter | Parameter type |
|---|---|---|
| Tabe | Address bus enable time | Maximum |
| Tabz | Address bus disable time | Maximum |
In Figure 7.3 DBE is HIGH and nENIN is LOW during the cycle shown.
The timing parameters used in Figure 7.3 are listed in Table 7.3.
Table 7.3. Bidirectional data write cycle timing parameters
| Symbol | Parameter | Parameter type |
|---|---|---|
| Tdoh | DOUT[31:0] hold from MCLKf | Minimum |
| Tdout | MCLKf to D[31:0] valid | Maximum |
| Tnen | MCLKf to nENOUT valid | Maximum |
| Tnenh | nENOUT hold time from MCLKf | Minimum |
In Figure 7.4, DBE is HIGH and nENIN is LOW during the cycle shown.
The timing parameters used in Figure 7.4 are listed in Table 7.4.
Table 7.4. Bidirectional data read cycle timing parameters
| Symbol | Parameter | Parameter type |
|---|---|---|
| Tbylh | BL[3:0] hold time from MCLKf | Minimum |
| Tbyls | BL[3:0] set up to from MCLKr | Minimum |
| Tdih | DIN[31:0] hold time from MCLKf | Minimum |
| Tdis | DIN[31:0] setup time to MCLKf | Minimum |
| Tnen | MCLKf to nENOUT valid | Maximum |
The cycle shown in Figure 7.5 is a data write cycle because nENOUT was driven LOW during phase one. Here, DBE has first been used to modify the behavior of the data bus, and then nENIN.
The timing parameters used in Figure 7.5 are listed in Table 7.5.
Table 7.5. Data bus control timing parameters
| Symbol | Parameter | Parameter type |
|---|---|---|
| Tdbe | Data bus enable time from DBEr | Maximum |
| Tdbnen | DBE to nENOUT valid | Maximum |
| Tdbz | Data bus disable time from DBEf | Maximum |
| Tdoh | DOUT[31:0] hold from MCLKf | Minimum |
| Tdout | MCLKf to D[31:0] valid | Maximum |
The timing parameters used in Figure 7.6 are listed in Table 7.6.
Table 7.6. Output 3-state time timing parameters
| Symbol | Parameter | Parameter type |
|---|---|---|
| Ttbe | Address and Data bus enable time from TBEr | Maximum |
| Ttbz | Address and Data bus disable time from TBEf | Maximum |
The timing parameters used in Figure 7.7 are listed in Table 7.7.
Table 7.7. Unidirectional data write cycle timing parameters
| Symbol | Parameter | Parameter type |
|---|---|---|
| Tdohu | DOUT[31:0] hold time from MCLKf | Minimum |
| Tdoutu | MCLKf to DOUT[31:0] valid | Maximum |
| Tnen | MCLKf to nENOUT valid | Maximum |
The timing parameters used in Figure 7.8 are listed in Table 7.8.
Table 7.8. Unidirectional data read cycle timing parameters
| Symbol | Parameter | Parameter type |
|---|---|---|
| Tbylh | BL[3:0] hold time from MCLKf | Minimum |
| Tbyls | BL[3:0] set up to from MCLKr | Minimum |
| Tdihu | DIN[31:0] hold time from MCLKf | Minimum |
| Tdisu | DIN[31:0] set up time to MCLKf | Minimum |
| Tnen | MCLKf to nENOUT valid | Maximum |
The timing parameters used in Figure 7.9 are listed in Table 7.9.
Table 7.9. Configuration pin timing parameters
| Symbol | Parameter | Parameter type |
|---|---|---|
| Tcth | Configurations hold time | Minimum |
| Tcts | Configuration setup time | Minimum |
In Figure 7.10, usually nMREQ and SEQ become valid Tmsd after the falling edge of MCLK. In this cycle the core has been busy-waiting for a coprocessor to complete the instruction. If CPA and CPB change during phase 1, the timing of nMREQ and SEQ depends on Tcpms. Most systems can generate CPA and CPB during the previous phase 2, and so the timing of nMREQ and SEQ is always Tmsd.
The timing parameters used in Figure 7.10 are listed in Table 7.10.
Table 7.10. Coprocessor timing parameters
| Symbol | Parameter | Parameter type |
|---|---|---|
| Tcph | CPA,CPB hold time from MCLKr | Minimum |
| Tcpi | MCLKf to nCPI valid | Maximum |
| Tcpih | nCPI hold time from MCLKf | Minimum |
| Tcpms | CPA, CPB to nMREQ, SEQ | Maximum |
| Tcps | CPA, CPB setup to MCLKr | Minimum |
In Figure 7.11, to guarantee recognition of the asynchronous interrupt (ISYNC=0) or reset source, the appropriate signals must be setup or held as follows:
setup Tis and Trs respectively before the corresponding clock edge
hold Tim and Tis respectively after the corresponding clock edge.
These inputs can be applied fully asynchronously where the exact cycle of recognition is unimportant.
The timing parameters used in Figure 7.11 are listed in Table 7.11.
Table 7.11. Exception timing parameters
| Symbol | Parameter | Parameter type |
|---|---|---|
| Tabth | ABORT hold time from MCLKf | Minimum |
| Tabts | ABORT set up time to MCLKf | Minimum |
| Tim | Asynchronous interrupt guaranteed nonrecognition time, with ISYNC=0 | Maximum |
| Tis | Asynchronous interrupt set up time to MCLKf for guaranteed recognition, with ISYNC=0 | Minimum |
| Trm | Reset guaranteed nonrecognition time | Maximum |
| Trs | Reset setup time to MCLKr for guaranteed recognition | Minimum |
The timing parameters used in Figure 7.12 are listed in Table 7.12.
Table 7.12. Synchronous interrupt timing parameters
| Symbol | Parameter | Parameter type |
|---|---|---|
| Tsih | Synchronous nFIQ, nIRQ hold from MCLKf with ISYNC=1 | Minimum |
| Tsis | Synchronous nFIQ, nIRQ setup to MCLKf, with ISYNC=1 | Minimum |
The timing parameters used in Figure 7.13 are listed in Table 7.13.
Table 7.13. Debug timing parameters
| Symbol | Parameter | Parameter type |
|---|---|---|
| Tbrkh | Hold time of BREAKPT from MCLKr | Minimum |
| Tbrks | Set up time of BREAKPT to MCLKr | Minimum |
| Tdbgd | MCLKr to DBGACK valid | Maximum |
| Tdbgh | DGBACK hold time from MCLKr | Minimum |
| Tdbgrq | DBGRQ to DBGRQI valid | Maximum |
| Texth | EXTERN[1:0] hold time from MCLKf | Minimum |
| Texts | EXTERN[1:0] set up time to MCLKf | Minimum |
| Trg | MCLKf to RANGEOUT0, RANGEOUT1 valid | Maximum |
| Trgh | RANGEOUT0, RANGEOUT1 hold time from MCLKf | Minimum |
| Trqh | DBGRQ guaranteed non-recognition time | Minimum |
| Trqs | DBGRQ set up time to MCLKr for guaranteed recognition | Minimum |
The timing parameter used in Figure 7.14 is listed in Table 7.14.
Table 7.14. DCC output timing parameters
| Symbol | Parameter | Parameter type |
|---|---|---|
| Tcommd | MCLKr to COMMRX, COMMTX valid | Maximum |
In Figure 7.15, BREAKPT changing in the LOW phase of MCLK (to signal a watchpointed store) affects nCPI, nEXEC, nMREQ, and SEQ in the same phase.
The timing parameter used in Figure 7.15 is listed in Table 7.15.
Table 7.15. Breakpoint timing parameters
| Symbol | Parameter | Parameter type |
|---|---|---|
| Tbcems | BREAKPT to nCPI, nEXEC, nMREQ, SEQ delay | Maximum |
In Figure 7.16, Tctdel is the delay, on either edge (whichever is greater), from the edge of TCK to ECLK.
The timing parameter used in Figure 7.16 is listed in Table 7.16.
Table 7.16. TCK and ECLK timing parameters
| Symbol | Parameter | Parameter type |
|---|---|---|
| Tctdel | TCK to ECLK delay | Maximum |
In Figure 7.17, the core is not clocked by the HIGH phase of MCLK when nWAIT is LOW. During the cycles shown, nMREQ and SEQ change once, during the first LOW phase of MCLK, and A[31:0] change once, during the second HIGH phase of MCLK. Phase 2 is shown for reference. This is the internal clock from which the core times all its activity. This signal is included to show how the HIGH phase of the external MCLK has been removed from the internal core clock.
The timing parameters used in Figure 7.17 are listed in Table 7.17.
Table 7.17. MCLK timing parameters
| Symbol | Parameter | Parameter type |
|---|---|---|
| Taddr | MCLKr to address valid | Maximum |
| Tmckh | MCLK HIGH time | Minimum |
| Tmckl | MCLK LOW time | Minimum |
| Tmsd | MCLKf to nMREQ and SEQ valid | Maximum |
| Twh | nWAIT hold from MCLKf | Minimum |
| Tws | nWAIT setup to MCLKr | Minimum |
The timing parameters used in Figure 7.18 are listed in Table 7.18.
Table 7.18. Scan general timing parameters
| Symbol | Parameter | Parameter type |
|---|---|---|
| Tbsch | TCK high period | Minimum |
| Tbscl | TCK low period | Minimum |
| Tbsdd | TCK to data output valid | Maximum |
| Tbsdh | Data output hold time from TCK | Minimum |
| Tbsih | TDI, TMS hold from TCKr | Minimum |
| Tbsis | TDI, TMS setup to TCKr | Minimum |
| Tbsod | TCKf to TDO valid | Maximum |
| Tbsoh | TDO hold time from TCKf | Minimum |
| Tbssh | I/O signal setup from TCKr | Minimum |
| Tbsss | I/O signal setup to TCKr, | Minimum |
The timing parameters used in Figure 7.19 are listed in Table 7.19.
Table 7.19. Reset period timing parameters
| Symbol | Parameter | Parameter type |
|---|---|---|
| Tbsr | nTRST reset period | Minimum |
| Trstd | nRESETf to D[31:0], DBGACK, nCPI, nENOUT, nEXEC, nMREQ, SEQ valid | Maximum |
| Trstl | nRESET LOW for guaranteed reset | Minimum |
Figure 7.20 shows the Tbse, output enable time, parameter and Tbsz, output disable time, when the HIGHZ TAP instruction is loaded into the instruction register.
The timing parameters used in Figure 7.20 are listed in Table 7.20.
Figure 7.21 shows the Tbse, output enable time, parameter and Tbsz, output disable time when data scanning, due to different logic levels being scanned through the scan cells for ABE and DBE.
The timing parameters used in Figure 7.21 are listed in Table 7.20.
Table 7.20. Output enable and disable timing parameters
| Symbol | Parameter | Parameter type |
|---|---|---|
| Tbse | Output enable time | Maximum |
| Tbsz | Output disable time | Maximum |
In Figure 7.22, Tald is the time by which ALE must be driven LOW to latch the current address in phase 2. If ALE is driven LOW after Tald, then a new address is latched. This is known as address breakthrough.
The timing parameters used in Figure 7.22 are listed in Table 7.21.
Table 7.21. ALE address control timing parameters
| Symbol | Parameter | Parameter type |
|---|---|---|
| Tald | Address group latch output time | Maximum |
| Tale | Address group latch open output delay | Maximum |
| Taleh | Address group latch output hold time | Minimum |
The timing parameters used in Figure 7.23 are listed in Table 7.22.
| Copyright © 2001, 2004 ARM Limited. All rights reserved. | ARM DDI 0210C |
| Non-Confidential | |
| PDF version | |
| Home > AC and DC Parameters > Timing diagrams |