ARM1136JF-S™ and ARM1136J-S™ Technical Reference Manual 3.3.23. c10, TEX remap registers

3.3.23. c10, TEX remap registers

The purpose of the TEX remap registers is to remap memory region attributes encoded by the TEX[2:0], C, and B bits in the page tables that are used by the MMU. For details of memory remap, see Memory region attributes.

Note

In addition to these TEX memory region remap registers, for other memory remap register descriptions see c15, Memory remap registers.

The TEX remap registers are:

in CP15 c10
two 32-bit read/write registers, described in the following sections:
- the Primary Region Remap Register, see Primary Region Remap Register (PRRR)
- the Normal Memory Remap Register, see Normal Memory Remap Register (NMRR)
see Accessing the TEX remap registers for more information about these registers
accessible in privileged mode only
only available from the rev1 (r1p0) release of the ARM1136JF-S processor.

These registers apply to all memory accesses and this includes accesses from the Data side, Instruction side, and DMA. Table 3.101 shows the purposes of the individual bits in the Primary Region Remap Register. Table 3.103 shows the purposes of the individual bits in the Normal Memory Remap Register.

Note

The behavior of the memory region remap registers depends on the TEX Remap Enable (TRE) bit, see c1, Control Register. If this bit is clear these registers do not have any effect. The TRE bit, and TEX remapping, are only implemented from the rev1 (r1p0) release of the ARM1136JF-S processor.

Primary Region Remap Register (PRRR)

This register is only available from the rev1 (r1p0) release of the ARM1136JF-S processor.

Figure 3.49 shows the arrangement of the bits in the register.

Figure 3.49. Primary Region Remap Register format

Table 3.101 shows the bit functions of the Primary Region Remap Register.

Table 3.101. Primary Region Remap Register bit functions

Bit range	Field name	Reset value^[1]	Function
[31:20]	-		UNP/SBZ
[19]	-	1	Remaps shareable attribute when S=1 for Normal regions^[2].
[18]	-	0	Remaps shareable attribute when S=0 for Normal regions^[2]
[17]	-	0	Remaps shareable attribute when S=1 for Device regions^[2]
[16]	-	1	Remaps shareable attribute when S= 0 for Device regions^[2]
[15:14]	-	b10	Remaps {TEX[0],C,B} = b111
[13:12]	-	b00	Remaps {TEX[0],C,B} = b110
[11:10]	-	b10	Remaps {TEX[0],C,B} = b101
[9:8]	-	b10	Remaps {TEX[0],C,B} = b100
[7:6]	-	b10	Remaps {TEX[0],C,B} = b011
[5:4]	-	b10	Remaps {TEX[0],C,B} = b010
[3:2]	-	b01	Remaps {TEX[0],C,B} = b001
[1:0]	-	b00	Remaps {TEX[0],C,B} = b000
^[1]The reset values ensure that no remapping occurs at reset. ^[2]Shareable attributes can map for both shared and non-shared memory. If the Shared bit read from the TLB or page tables is 0, then the bit remaps to the Not Shared attributes in this register. If the Shared bit read from the TLB or page tables is 1, then the bit remaps to the Shared attributes of this register. See Remapped region cache attribute encodings for more information.

Table 3.102 shows the encoding of the remapping for the primary memory type.

Table 3.102. Encoding for the remapping of the primary memory type

Encoding	Memory type
b00	Strongly ordered
b01	Device
b10	Normal
b11	UNP (Normal)

Normal Memory Remap Register (NMRR)

This register is only available from the rev1 (r1p0) release of the ARM1136JF-S processor.

Figure 3.50 shows the arrangement of the bits in the register.

Figure 3.50. Normal Memory Remap Register format

Table 3.103 shows the bit functions of the Normal Memory Remap Register.

Table 3.103. Normal Memory Remap Register bit functions

Bit range	Field name	Reset value^[1]	Function
[31:30]	-	b01	Remaps Outer attribute for {TEX[0],C,B} = b111
[29:28]	-	b00	Remaps Outer attribute for {TEX[0],C,B} = b110
[27:26]	-	b01	Remaps Outer attribute for {TEX[0],C,B} = b101
[25:24]	-	b00	Remaps Outer attribute for {TEX[0],C,B} = b100
[23:22]	-	b11	Remaps Outer attribute for {TEX[0],C,B} = b011
[21:20]	-	b10	Remaps Outer attribute for {TEX[0],C,B} = b010
[19:18]	-	b00	Remaps Outer attribute for {TEX[0],C,B} = b001
[17:16]	-	b00	Remaps Outer attribute for {TEX[0],C,B} = b000
[15:14]	-	b01	Remaps Inner attribute for {TEX[0],C,B} = b111
[13:12]	-	b00	Remaps Inner attribute for {TEX[0],C,B} = b110
[11:10]	-	b10	Remaps Inner attribute for {TEX[0],C,B} = b101
[9:8]	-	b00	Remaps Inner attribute for {TEX[0],C,B} = b100
[7:6]	-	b11	Remaps Inner attribute for {TEX[0],C,B} = b011
[5:4]	-	b10	Remaps Inner attribute for {TEX[0],C,B} = b010
[3:2]	-	b00	Remaps Inner attribute for {TEX[0],C,B} = b001
[1:0]	-	b00	Remaps Inner attribute for {TEX[0],C,B} = b000
^[1]The reset values ensure that no remapping occurs at reset.

Table 3.104 shows the encoding for the Inner or Outer cachable attribute bit fields I0 to I7 and O0 to O7.

Table 3.104. Remap encoding for Inner or Outer cachable attributes

Encoding	Cachable attribute
b00	Noncachable
b01^[1]	Write-back, allocate on write
b10	Write-through, no allocate on write
b11	Write-back, no allocate on write
^[1]Not allowed for inner cache attributes. The ARM1136JF-S processor does not support write-allocate on inner caches.

Accessing the TEX remap registers

Table 3.105 shows the results of attempted accesses to the TEX remap registers for each mode.

Table 3.105. Results of access to the memory region remap registers

Privileged read	Privileged write	User
Data read	Data write	Undefined exception

To access the TEX remap registers you read or write CP15 with:

Opcode_1 set to 0
CRn set to c10
CRm set to c2
Opcode_2 set to:
- 0, Primary Region Remap Register
- 1, Normal Memory Remap Register.

For example:

MRC p15, 0, <Rd>, c10, c2, 0     ; Read Primary Region Remap Register (PRRR)

MCR p15, 0, <Rd>, c10, c2, 0     ; Write Primary Region Remap Register (PRRR)

MRC p15, 0, <Rd>, c10, c2, 1     ; Read Normal Memory Remap Register (NMRR)

MCR p15, 0, <Rd>, c10, c2, 1     ; Write Normal Memory Remap Register (NMRR)

Using the TEX remap registers

Memory remap occurs in two stages:

The processor uses the Primary Region Remap Register to remap the primary memory type, Normal, Device, or Strongly Ordered, and the shareable attribute.
For memory regions that the Primary Region Remap Register defines as Normal memory, the processor uses the Normal Memory Remap Register to remap the inner and outer cachable attributes.

The behavior of the memory region remap registers depends on the TEX Remap bit, see c1, Control Register. If the TEX Remap bit is set to 1, the entries in the memory region remap registers remap each possible value of the TEX[0], C and B bits in the page tables. You can therefore set your own definitions for these values. This remapping is shown in Table 3.106.

Table 3.106. Page table format TEX[0], C and B bit encodings when TRE=1^[1]

Page Table encodings			Remapped memory type	When memory type remapped as Normal
TEX[0]	C	B	Remapped memory type	Inner cache attributes	Outer cache attributes
0	0	0	PRRR[1:0]	NMRR[1:0]	NMRR[17:16]
0	0	1	PRRR[3:2]	NMRR[3:2]	NMRR[19:18]
0	1	0	PRRR[5:4]	NMRR[5:4]	NMRR[21:20]
0	1	1	PRRR[7:6]	NMRR[7:6]	NMRR[23:22]
1	0	0	PRRR[9:8]	NMRR[9:8]	NMRR[25:24]
1	0	1	PRRR[11:10]	NMRR[11:10]	NMRR[27:26]
1	1	0	PRRR[13:12]	NMRR[13:12]	NMRR[29:28[
1	1	1	PRRR[15:14]	NMRR[15:14]	NMRR[31:30]

If the TEX Remap bit is set to 0, the memory region remap registers are not used and no memory remapping takes place. For more information see Memory region attributes.

The memory region remap registers are expected to remain static during normal operation. When you write to the memory region remap registers, you must invalidate the TLB and perform an IMB operation before you can rely on the new written values. You must also stop the DMA if it is running or queued.

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