ARM1136JF-S™ and ARM1136J-S™ Technical Reference Manual 3.3.4. c0, TLB Type Register

3.3.4. c0, TLB Type Register

The purpose of the TLB Type Register is to return the number of lockable entries for the TLB.

The TLB has 64 entries organized as a unified two-way set associative TLB. In addition, it has eight lockable entries, specified by the read-only TLB Type Register.

The TLB Type Register is:

in CP15 c0
a 32-bit read only register
accessible in privileged mode only.

Figure 3.13 shows the arrangement of bits in the register.

Figure 3.13. TLB Type Register format

Table 3.16 lists the bit functions of the TLB Type Register.

Table 3.16. TLB Type Register field descriptions

Bits	Field	Description
[31:24]	-	SBZ/UNP.
[23:16]	ILsize	Specifies the number of instruction TLB lockable entries. For ARM1136JF-S processors this is 0.
[15:8]	DLsize	Specifies the number of unified or data TLB lockable entries. For ARM1136JF-S processors this is 8.
[7:1]	-	SBZ/UNP.
[0]	U	Specifies if the TLB is unified (0), or if there are separate instruction and data TLBs (1). For ARM1136JF-S processors this is 0.

Accessing the TLB Type Register

Table 3.17 shows the results of attempted accesses to the TLB Type Register for each mode.

Table 3.17. Results of accesses to the TCM Status Register

Privileged read	Privileged write	User read or write
Data read	Undefined exception	Undefined exception

To access the TLB Type Register you read CP15 c0 with:

Opcode_1 set to 0
CRn set to c0
CRm set to c0
Opcode_2 set to 3.

For example:

MRC p15,0,<Rd>,c0,c0,3                     ; returns TLB details

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