ARM1136JF-S™ and ARM1136J-S™ Technical Reference Manual 3.3.25. c11, DMA Identification and Status Registers

The purpose of the DMA identification and status registers is to define:

Processes that handle DMA can read these registers to determine the physical resources implemented and their availability.

The DMA Identification and Status Registers are:

Figure 3.51 shows the arrangement of bits in the DMA Identification and Status Registers 0 to 3.

Figure 3.51. DMA Identification and Status Registers format

Table 3.108 shows the bit functions of the DMA Identification and Status Registers.

Table 3.108. DMA identification and status register bit functions

Bit range	Field name	Function
[31:2]	-	UNP/SBZ.
[1]	CH1	Provides information on DMA Channel 1 functions. 0 = DMA Channel 1 function^[1] disabled 1 = DMA Channel 1 function^[1] enabled.
[0]	CH0	Provides information on DMA Channel 0 functions. 0 = DMA Channel 0 function^[1] disabled 1 = DMA Channel 0 function^[1] enabled.
^[1]Table 3.109 lists the channel functions that correspond to different values of Opcode_2 in the MRC instruction.

The Channel bits of each register, bits 0 and 1, correspond to the two channels that are defined architecturally:

Table 3.109 shows the Opcode_2 values used to identify the registers implemented and register status.

Table 3.109. DMA Identification and Status Register functions

Opcode_2	Function
0	Present: 1 = the channel is Present 0 = the channel is not Present.
1	Queued: 1 = the channel is Queued 0 = the channel is not Queued.
2	Running: 1 = the channel is Running 0 = the channel is not Running.
3	Interrupting: 1 = the channel is Interrupting (through completion or an error) 0 = the channel is not Interrupting.
4-7	Reserved. Unpredictable.

Table 3.110 shows the results of attempted accesses to the DMA Identification and Status Registers for each mode.

Table 3.110. Results of accesses to the DMA Identification and Status Registers

Privileged read	Privileged write	User read or write
Data read	Undefined exception	Undefined exception

To access the DMA Identification and Status Registers you read CP15 with:

Opcode_1 set to 0
CRn set to c11
CRm set to c0
Opcode_2 set to:
- 0, for the Present function
- 1, for the Queued function
- 2, for the Running function
- 3, for the Interrupting function.

For example:

            MRC p15, 0, <Rd>, c11, c0, 0     ; Read DMA Identification and Status Register present

            MRC p15, 0, <Rd>, c11, c0, 1     ; Read DMA Identification and Status Register queued

            MRC p15, 0, <Rd>, c11, c0, 2     ; Read DMA Identification and Status Register running

            MRC p15, 0, <Rd>, c11, c0, 3     ; Read DMA Identification and Status Register interrupting

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