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The purpose of the Translation Table Base Control Register is to determine whether a page table miss for a specific Virtual Address uses Translation Table Base Register 0 or Translation Table Base Register 1.
Use of Translation Table Base Register 0 is recommended for task-specific addresses.
Use of Translation Table Base Register 1 is recommended use for operating system and I/O addresses.
The Translation Table Base Control Register is:
in CP15 c2
a 32 bit read/write register
accessible in privileged mode only.
Figure 3.31 shows the arrangement of bits in the register.
Figure 3.31 shows that there is a single bit field in the register. This holds a three-bit value, N. When N is greater than zero it specifies the boundary size of the Transition Table Base Register 0, see c2, Translation Table Base Register 0, TTBR0. Table 3.56 shows the meaning of different values of N.
Table 3.56. Values of N for Translation Table Base Register 0
| N | Translation Table Base Register 0 page table boundary size |
|---|---|
| 0 | 16KB |
| 1 | 8KB |
| 2 | 4KB |
| 3 | 2KB |
| 4 | 1KB |
| 5 | 512-byte |
| 6 | 256-byte |
| 7 | 128-byte |
Table 3.57 shows the results of attempted accesses to the Translation Table Base Control Register for each mode.
Table 3.57. Results of accesses to the Translation Table Base Control Register
| Privileged read | Privileged write | User read or write |
|---|---|---|
| Data read | Data write | Undefined exception |
To access the Translation Table Base Control Register you read or write CP15 with:
Opcode_1 set to 0
CRn set to c2
CRm set to c0
Opcode_2 set to 2.
For example:
MRC p15, 0, <Rd>, c2, c0, 2 ; Read Translation Table Base Control Register
MCR p15, 0, <Rd>, c2, c0, 2 ; Write Translation Table Base Control Register
Reading from CP15 c2 returns the size of the page table boundary for Translation Table Base Register 0. Bits [31:3] Read As Zero.
Writing to CP15 c2 updates the size, N, of the first-level translation table base boundary for Translation Table Base Register 0.
The Translation Table Base Register is selected as follows:
If N = 0, always use Translation Table Base Register 0.
This is the default case at reset. It is backwards compatible with ARMv5 or earlier processors.
If N is greater than 0, then:
if bits [31:32-N] of the Virtual Address are all 0, use Translation Table Base Register 0
otherwise use Translation Table Base Register 1.
N must be in the range 0 to 7.
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