ARM1136JF-S™ and ARM1136J-S™ Technical Reference Manual 13.5. CP14 debug instructions

13.5. CP14 debug instructions

Table 13.28 shows the CP14 debug instructions.

Table 13.28. CP14 debug instructions

Binary address		Register number	Abbreviation	Legal instructions
Opcode_2	CRm	Register number	Abbreviation	Legal instructions
b000	b0000	0	DIDR	`MRC p14, 0, <Rd>, c0, c0, 0`^[1]
b000	b0001	1	DSCR	`MRC p14, 0, <Rd>, c0, c1,0`^[1] `MRC p14, 0, R15, c0, c1,0` `MCR p14, 0, <Rd>, c0, c1,0`^[1]
b000	b0101	5	DTR (rDTR/wDTR)	`MRC p14, 0, <Rd>, c0, c5, 0`^[1] `MCR p14, 0, <Rd>, c0, c5, 0`^[1] `STC p14, c5, <addressing mode>` `LDC p14, c5, <addressing mode>`
b000	b0111	7	VCR	`MRC p14, 0, <Rd>, c0, c7, 0`^[1] `MCR p14, 0, <Rd>, c0, c7, 0`^[1]
b100	b0000-b1111	64-79	BVR	`MRC p14, 0, <Rd>, c0, cy,4`^[1]^,^[2] `MCR p14, 0, <Rd>, c0, cy,4`^[1]^,^[2]
b101	b0000-b1111	80-95	BCR	`MRC p14, 0, <Rd>, c0, cy,5`^[1]^,^[2] `MCR p14, 0, <Rd>, c0, cy,5`^[1]^,^[2]
b110	b0000-b1111	96-111	WVR	`MRC p14, 0, <Rd>, 0, cy, 6`^[1]^,^[2] `MCR p14, 0, <Rd>, 0, cy, 6`^[1]^,^[2]
b111	b0000-b1111	112-127	WCR	`MRC p14, 0, <Rd>, c0, cy, 7`^[1]^,^[2] `MCR p14, 0, <Rd>, c0, cy, 7`^[1]^,^[2]
^[1]`<Rd>` is any of the ARM registers R0-14. ^[2]y is the decimal representation for the binary number CRm.

In Table 13.28, MRC p14,0,<Rd>,c0,c5,0 and STC p14,c5,<addressing mode> refer to the rDTR and MCR p14,0,<Rd>,c0,c5,0 and LDC p14,c5,<addressing mode> refer to the wDTR. See CP14 c5, Data Transfer Registers (DTR) for more details.

The MRC p14,0,R15,c0,c1,0 instruction sets the CPSR flags as follows:

N flag = DSCR[31]. This is an Unpredictable value.
Z flag = DSCR[30]. This is the value of the rDTRfull flag.
C flag = DSCR[29]. This is the value of the wDTRfull flag.
V flag = DSCR[28]. This is an Unpredictable value.

Instructions that follow the MRC instruction can be conditioned to these CPSR flags.

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