The ARM1136JF-S processor includes these instructions in addition to those defined in the ARMv6 architecture:
Load Register Exclusive instructions, see LDREXB, LDREXH, and LDREXD
Store Register Exclusive instructions, see STREXB, STREXH, and STREXH
Clear Register Exclusive instruction, see CLREX
No Operation instruction, see NOP - True No Operation.
These instructions were introduced in rev1 of the ARM1136JF-S processor (r1p0).