16.9. Processor state updating instructions
This section describes the cycle timing behavior for the MSR,
MRS, CPS, and SETEND instructions. Table 16.12 shows processor state updating instructions
and their cycle timing behavior.
Table 16.12. Processor state updating instructions cycle timing behavior
| Instruction | Cycles | Comments |
|---|
MRS | 1 | All MRS instructions |
MSR CPSR_f | 1 | MSR to CPSR flags only |
MSR | 4 | All other MSRs to the CPSR |
MSR SPSR | 5 | All MSRs to the SPSR |
CPS <effect> <iflags> | 1 | Interrupt masks only |
CPS <effect> <iflags>, #<mode> | 2 | Mode changing |
SETEND | 1 | - |
PDF version