16.14. Synchronization instructions
This section describes the cycle timing behavior for the SWP,
SWPB, CLREX and the load and store exclusive instructions.
In all cases the base register, Rn, is an Early Reg, and requires
an extra cycle of result latency to provide its value. Table 16.21 shows the synchronization
instructions cycle timing behavior.
Table 16.21. Synchronization instructions cycle timing behavior
| Instruction | Cycles | Memory cycles | Result latency |
|---|
SWP Rd, <Rm>, [Rn] | 2 | 2 | 3 |
SWPB Rd, <Rm>, [Rn] | 2 | 2 | 3 |
LDREX <Rd>, [Rn] | 1 | 1 | 3 |
STREX, Rd>, <Rm>, [Rn] | 1 | 1 | 3 |
LDREXB <Rd>, [Rn][1] | 1 | 1 | 3 |
STREXB, Rd>, <Rm>, [Rn][1] | 1 | 1 | 3 |
LDREXH <Rd>, [Rn][1] | 1 | 1 | 3 |
STREXH, Rd>, <Rm>, [Rn][1] | 1 | 1 | 3 |
LDREXD <Rd>, [Rn][1] | 1 | 1 | 3 |
STREXD, Rd>, <Rm>, [Rn][1] | 1 | 1 | 3 |
CLREX[1] | 1 | 1 | X |
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