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Access Flag faults are only defined from the rev1 (r1p0) release of the ARM1136JF-S processor, and the Access Flag Enable bit is not defined in rev0 RTL releases.
The Access Flag Enable (AFE) bit is bit [29] of the CP15 Control Register, see c1, Control Register. When this bit is set, AP[0] indicates if there is an Access Flag fault.
The AFE bit is only taken into account when the XP bit, bit [23], in the CP15 Control Register is set. Setting the XP bit disables the subpage AP bits. This mode (XP=1) is referred to as ARMv6 mode.
In the configuration XP=1 and AFE=1, the OS uses only bits APX and AP[1] as Access Permission bits, and AP[0] becomes an Access Flag, see Access permissions. The Access Flag records recent TLB access to a page, or section, and the OS can use this to optimize memory managements algorithms. In particular, the flag can be used to identify when a page or section is accessed for the first time.
In the ARM1136JF-S processor the Access Flag must be managed by the software.
Reading a page table entry into the TLB when the Access Flag is 0 causes an Access Flag fault. This fault is readily distinguished from other faults that the TLB generates and this permits fast setting of the Access Flag in software.
The processor can generate two kind of Access Flag faults:
a Section Access Flag fault, when the access flag, AP[0], is contained in a first level translation table descriptor
a Page Access Flag fault, when the access flag, AP[0], is contained in a second level translation table descriptor.
It is architecturally Unpredictable whether the TLB caches the effect of the AFE bit on page tables. This means that when you change the AFE bit you must invalidate the TLB before you rely on the effect of the new value of the AFE bit.