ARM1136JF-S™ and ARM1136J-S™ Technical Reference Manual Chapter 16. Cycle Timings and Interlock Behavior

Chapter 16. Cycle Timings and Interlock Behavior

This chapter describes the cycle timings and interlock behavior of integer instructions on the ARM1136JF-S processor. It contains the following sections:

About cycle timings and interlock behavior
Register interlock examples
Data processing instructions
QADD, QDADD, QSUB, and QDSUB instructions
ARMv6 media data processing
ARMv6 Sum of Absolute Differences (SAD)
Multiplies
Branches
Processor state updating instructions
Single load and store instructions
Load and store double instructions
Load and store multiple instructions
RFE and SRS instructions
Synchronization instructions
Coprocessor instructions
No operation instruction
SWI, BKPT, Undefined, and Prefetch Aborted instructions
Thumb instructions.

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