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The purpose of the Cache Operations Register, c7, is to:
control these operations:
clean and invalidate instruction and data caches, including range operations
prefetch instruction cache line
flush prefetch buffer
flush branch target address cache
data synchronization barrier
stop prefetch range
access these registers:
Cache Dirty Status Register
Block Transfer Status Register
implement the Data Memory Barrier (DMB) operation
implement the Wait For Interrupt clock control function
perform block transfers operations, using the MCRR operation.
Cache operations also depend on:
the C, I and RR bits, see c1, Control Register
the RA and RV bits, see c1, Auxiliary Control Register.
The Cache Operations Register, c7, consists of one 32-bit register that performs 29 functions, including providing access to two other registers.
Figure 3.35 shows the arrangement of the 23 functions
in this group that operate with the MCR and MRC instructions.
Figure 3.36 shows
the arrangement of the 6 functions in this group that operate with
the MCRR instruction.
Most of the CP15 c7 operations are write-only, and can only be performed when in privileged mode. Full details of the results of attempting to perform the CP15 c7 operations from each mode are given in the following sections:
The following operations are write-only, and can only be performed when in privileged mode:
Wait For Interrupt
Invalidate Entire Instruction Cache
Invalidate Instruction Cache, using MVA
Invalidate Instruction Cache, using Set/Way
Flush Entire Branch Target Cache
Flush Branch Target Cache Entry
Invalidate Entire Data Cache
Invalidate Data Cache Line, using MVA
Invalidate Data Cache Line, using Set/Way
Invalidate Both Data Caches
Clean Entire Data Cache
Clean Data Cache Line, using MVA
Clean Data Cache Line, using Set/Way
Prefetch Instruction Cache Line
Clean and Invalidate Entire Data Cache
Clean and Invalidate Data Cache Line, using MVA
Clean and Invalidate Data Cache Line, using Set/Way.
Table 3.69 shows the results of attempting these operations for each mode.
There is one read-only privileged mode operation:
Read Cache Dirty Status Register.
Table 3.70 shows the results of attempting this operation for each mode.
The following write-only operations can be executed in User mode:
Flush Prefetch Buffer
Data Synchronization Barrier
Data Memory Barrier
Stop Prefetch Range.
Table 3.71 shows the results of attempting these operations for each mode.
There is one read-only operation that can be executed in User mode:
Read Block Transfer Status Register.
Table 3.72 shows the results of attempting this operation for each mode.
Attempting to access c7 with a Opcode_1, CRm and Opcode_2 combinations not shown in Figure 3.35 or Figure 3.36 results in an Undefined Instruction exception, except for the following operations in privileged mode:
MCR
p15,0,<Rd>,c7,c7,{1-7}
MCR p15,0,<Rd>,c7,c11,{0-7}
MCR p15,0,<Rd>,c7,c15,{0-7}.
These operations are architecturally defined as unified cache operations. The ARM1136JF-S processor has separate caches, and unified cache operations are treated as NOPs.
Attempting to perform these operations from User mode will result in an Undefined Instruction exception.
There are three ways to use c7:
If you want to access the Cache Dirty
Status Register or the Block Transfer Status Register, you use the MRC instruction
to read c7.
These registers are both read-only.
To perform a range operation you use the MCRR instruction
to write to c7, with Opcode_1 and CRm set to the values needed to
select the required operation.
To perform any other operation you use the MCR instruction,
with Opcode_1 = 0, to write to c7. You set CRm and Opcode_2 to select
the required operation.
For write operations using MCR, <Rd> will
be one of:
a Virtual Address (VA)
a Modified Virtual Address (MVA)
Way and Set
zero, for Should Be Zero (SBZ) operations.
Figure 3.35 shows the type of argument needed by each of the c7 operations.
For write operations using MCRR, <Rd> and <Rn> will
both be virtual addresses, as shown in Figure 3.36.
More information about the CP15 c7 operations is given in the following sections:
The purposes of the invalidate, clean, and prefetch operations that c7 provides are to:
Invalidate part or all of the Data or Instruction caches
Clean part or all of the Data cache
Clean and Invalidate part or all of the Data cache
Prefetch code into the Instruction cache.
The terms used to describe the invalidate, clean, and prefetch operations are defined in the Caches and Write Buffers chapter of the ARM Architecture Reference Manual.
When it controls invalidate, clean, and prefetch operations, c7 appears as a 32-bit write only register. There are three possible formats for the data that you write to the register. The format you need depends on the specific operation:
Way and Set format, described in the section Way and Set format
MVA, described in the section MVA format
SBZ.
Way and Set format is used for these c7 operations:
Invalidate Instruction Cache Line, using Set/Way
Invalidate Data Cache Line, using Set/Way
Clean Data Cache Line, using Set/Way
Clean and Invalidate Data Cache Line, using Set/Way.
Figure 3.37 shows the Way and Set tag format you use to specify the line in the cache that you want to access.
Table 3.73 shows the bit fields for Way and Set operations using CP15 c7, and their meanings.
Table 3.73. Bit fields for Way and Set operations using CP15 c7
Bits | Name | Description |
|---|---|---|
[31:30] | Way | Way in set being accessed |
[29:S+3] | - | SBZ/UNP |
[S+2:5] | Set | Set being accessed |
[4:1] | - | SBZ/UNP |
| [0] | TC | Tightly-Coupled memory operation 0 = Cache operation 1 = TCM operation |
When using Set/Way format, the size of the Set field in the register, and so the value of S in Table 3.73, depends on the cache size. Table 3.74 shows the relationship of the S parameter value to the cache size.
The value of S is derived from the following equation:
See c0, Cache Type Register for more information about instruction and data cache size.
Figure 3.35 identifies which c7 operations require you to use the Way and Set register format. In these operations, the register identifies the cache line to which the operation applies by specifying: which cache Set it belongs to, and its Way within that Set.
which cache Set it belongs to
its Way number within that Set.
The MVA format is useful for flushing a particular address or range of addresses in the caches. Figure 3.38 shows the MVA format for these c7 operations:
Invalidate Instruction Cache Line, using MVA
Invalidate Data Cache Line, using MVA
Clean Data Cache Line, using MVA
Prefetch Instruction Cache Line
Clean and Invalidate Data Cache Line, using MVA.
With these operations, bits[4:0] are ignored.
Figure 3.39 shows the MVA format for the c7 Flush Branch Target Cache Entry operation.
With the Flush Branch Target Cache Entry operation, bits[2:0] are ignored.
Table 3.75 shows the bit fields for MVA operations using CP15 c7, and their meanings.
Table 3.75. Bit fields for MVA operations using CP15 c7
Bits | Name | Description |
|---|---|---|
[31:N+1][1] | MVA | Specifies address to invalidate, clean, or prefetch. Holds the MVA of the cache line. |
[N:0][1] | - | SBZ/UNP. |
[1] For the Flush Branch Target Cache Entry operation N=2. For all other MVA operations, N=4. | ||
For the cache control operations, the MVAs that are passed to the cache are not translated by the FCSE extension.
Table 3.76 shows the instructions and operations that you can use to clean and invalidate an entire cache. For all of these operations the value in c7 SBZ.
Table 3.76. Cache operations for entire cache
Instruction | Data | Function |
|---|---|---|
| SBZ | Invalidate Entire Instruction Cache. Also flushes the branch target cache. |
| SBZ | Invalidate Entire Data Cache. |
| SBZ | Invalidate Both Caches. Also flushes the branch target cache. |
| SBZ | Clean Entire Data Cache. |
MCR p15, 0, <Rd>, c7, c14, 0 | SBZ | Clean and Invalidate Entire Data Cache. |
The operations for cleaning the entire Data Cache, and also for performing a clean and invalidate of the entire Data Cache, are blocking operations that can be interrupted. If they are interrupted, the r14 value that is captured on the interrupt is:
(address of the instruction that launched the cache clean operation) + 4
This enables the standard return mechanism for interrupts to restart the operation.
If it is essential that the cache is clean for a particular operation, the sequence of instructions for cleaning the cache for that operation must handle the arrival of an interrupt at any time when interrupts are not disabled. This requirement also applies to cache clean and invalidate, and is because interrupts can write to a previously clean cache. You can interrogate the Cache Dirty Status Register to determine if the cache is clean. If you do this with interrupts disabled, and the returned value shows the cache to be clean, the following operation can rely on having a clean cache.
Example 3.1 shows this approach:
Example 3.1. Ensuring the cache is clean
; interrupts are assumed to be enabled at this point
Loop1 MOV R1, #0
MCR CP15, 0, R1, C7, C10, 0 ; Clean (or Clean & Invalidate) Cache
MRS R2, CPSR
CPSID iaf ; Disable interrupts
MRC CP15, 0, R1, C7, C10, 6 ; Read Cache Dirty Status Register
ANDS R1, R1, #01 ; Check if it is clean
BEQ UseClean
MSR CPSR, R2 ; Re-enable interrupts
B Loop1 ; - clean the cache again
UseClean Do_Clean_Operations ; Perform whatever operation relies on
; the cache being clean/invalid.
; To reduce impact on interrupt
; latency, this sequence should be
; short
MSR CPSR, R2 ; Re-enable interrupts
The long cache clean operation is performed with interrupts enabled throughout this routine.
The Clean Entire Data Cache operation and Clean and Invalidate Entire Data Cache operation have no effect on TCMs operating as SmartCache.
There are two ways to perform invalidate or clean operations on cache lines:
by use of Way and Set format
by use of MVA format.
Table 3.77 shows the instructions and operations that you can use for single cache lines.
Table 3.77. Cache operations for single lines
Instruction | Data | Function |
|---|---|---|
| MVA | Invalidate Instruction Cache Line, using MVA. |
| Set/Way | Invalidate Instruction Cache Line, using Set/Way. |
| MVA | Invalidate Data Cache Line, using MVA. |
MCR p15, 0, <Rd>, c7, c6, 2 | Set/Way | Invalidate Data Cache Line, using Set/Way. |
| MVA | Clean Data Cache Line, using MVA. |
| Set/Way | Clean Data Cache Line, using Set/Way. |
| MVA | Prefetch Instruction Cache Line. |
| MVA | Clean and Invalidate Data Cache Line, using MVA. |
| Set/Way | Clean and Invalidate Data Cache Line, using Set/Way. |
Example 3.2 shows how to use Clean and Invalidate Data Cache Line with Way and Set to clean and invalidate one whole cache way, in this example, way 3. The example works with any cache size because it reads the cache size from the Cache Type Register.
Example 3.2. Clean and Invalidate Data Cache Line, using Way and Set
MRC p15,0,r0,c0,c0,1 ; Read cache type reg
AND r0,r0,#0x1C0000 ; Extract D cache size
MOV r0,r0, LSR #18 ; Move to bottom bits
ADD r0,r0,#7 ; Get Index loop max
MOV r1,#3:SHL:30 ; Set up Set = 3
MOV r2,#0 ; Set up Index counter
MOV r3,#1
MOV r3,r3, LSL r0 ; Set up Index loop max
index_loop
ORR r4,r2,r1 ; Way and Set format
MCR p15,0,r4,c7,c14,2 ; Clean&inval D cache line
ADD r2,r2,#1:SHL:5 ; Increment Index
CMP r2,r3 ; Done all index values?
BNE index_loop ; Loop until done
Table 3.78 shows the operations that you can use to clean and invalidate the address ranges in cache, and to prefetch to the instruction or data cache. These operations are performed using an MCRR instruction. All other MCRR accesses to CP15 are ignored.
Table 3.78. Cache operations for address ranges
| Instruction | Data | Function |
|---|---|---|
| VA | Invalidate Instruction Cache Range. |
| VA | Invalidate Data Cache Range. |
| VA | Clean Data Cache Range[1]. |
| VA | Clean and Invalidate Data Cache Range. |
| VA | Prefetch Instruction Cache Range[1]. |
| VA | Prefetch Data Cache Range[1]. |
[1] These operations are accessible in both User and privileged mode of operation. The other operations listed here are only accessible in privileged mode. | ||
The End Address and Start Address in Table 3.78 are the true VAs
before any modification by the Fast Context Switch Extension (FCSE).
These addresses are translated by the FCSE logic. Figure 3.40 shows the block
address format of the Start Address and End
Address data values passed by the MCRR instructions.
Each of the range operations operates between cache lines,
or SmartCache lines, containing the Start Address and
the End Address, inclusive of Start
Address and End Address. Because the
least significant address bits are ignored, as shown in Figure 3.40, the transfer
automatically adjusts to a line length multiple spanning the programmed addresses:
The Start Address is
the first VA of the block transfer. It uses the VA bits [31:5].
The End Address
If the Start Address is greater than the End Address the effect is architecturally Unpredictable. The ARM1136JF-S processor does not perform a cache operation in this case.
Table 3.79 summarizes these CP15 c7 block operations.
Table 3.79. CP15 c7 block transfer operations
| Operation | Blocking? | Instruction or data | User or privileged | Exception behavior |
|---|---|---|---|---|
| Prefetch Range | Nonblocking | Instruction or data | User or privileged | None |
| Clean Range | Blocking | Data | User or privileged | Data Abort |
| Clean and Invalidate Range | Blocking | Data only | Privileged | Data Abort |
| Invalidate Range | Blocking | Instruction or data | Privileged | Data Abort |
Only one block transfer at a time is supported. Attempting to start a second block transfer while a first nonblocking block transfer is in progress causes the first block transfer to be abandoned and the second block transfer to be started. The Block Transfer Status Register indicates if a block transfer is in progress. Block transfers must be stopped on a context switch. You can stop a prefetch range operation using the Stop Prefetch Range operation, as listed in Figure 3.35.
All block transfers are interruptible. When blocking transfers are interrupted, the r14 value that is captured is: (address of the instruction that launched the block operation) + 4 This enables the standard return mechanism for interrupts to restart the operation.
ARM1136JF-S processors enable following instructions to be executed while a nonblocking Prefetch Range instruction is being executed. The r14 value captured on an interrupt is determined by the execution state presented to the interrupt in following instruction stream.
If the FCSE PID is changed while a Prefetch Range operation is running, it is Unpredictable at which point this change is seen by the Prefetch Range.
The blocking block transfers cause a Data Abort on a translation fault if a valid page table entry cannot be fetched. The FAR indicates the address that caused the fault, and the DFSR indicates the reason for the fault.
Any fault on a Prefetch Range operation results in the operation failing without signaling an error.
All cache line and block cleaning and invalidation operations based on Virtual Address, as defined in CP15 c7, include TCM regions that are configured as SmartCache.
The Set/Way operations are supported for the TCMs operating as SmartCache. In this case, the Way number is taken to be the TCM number, and the meaning of the set number is unchanged. Figure 3.37 shows how the bottom bit of the Set/Way is used to distinguish between Set/Way operations applied to the cache and Set/Way operations applied to TCM.
The line length of the TCM operating as SmartCache must be the same as the cache line length, defined in the Cache Type Register.
The TC bit, bit 0, indicates if this register is ring to the TCMs rather than the cache:
Register s to the cache.
Register s to the TCM.
Invalidate and Clean Entire Cache operations do not affect the TCMs.
The purpose of the Cache Dirty Status Register is to indicate when the Cache is dirty.
The Cache Dirty Status Register is:
in CP15 c7
a 32-bit read only register
accessible in privileged mode only.
Figure 3.41 shows the arrangement of bits in the Register.
Table 3.80 shows the bit functions of the Cache Dirty Status Register.
Table 3.80. Cache Dirty Status Register bit functions
Bit range | Field name | Function |
|---|---|---|
[31:1] | - | RAZ |
| [0] | C | The C bit indicates if the cache is dirty. 0 indicates that no write has hit the cache since the last cache clean, clean and invalidate, or invalidate all operation, or reset, successfully left the cache clean. This is the reset value. 1 indicates that the cache might contain dirty data. |
Table 3.81 shows the results of attempted accesses to the Cache Dirty Status Register for each mode.
Table 3.81. Results of accesses to the Main ID Register
| Privileged read | Privileged write | User read or write |
|---|---|---|
| Data read | Undefined exception | Undefined exception |
To access the Main ID Register you read CP15 with:
Opcode_1 set to 0
CRn set to c7
CRm set to c10
Opcode_2 set to 6.
For example:
MRC p15, 0, <Rd>, c7, c10, 6 ; Read Cache Dirty Status Register
Table 3.82 shows the flush operations and instructions available through c7.
Table 3.82. Cache operations flush functions
Instruction | Data | Function |
|---|---|---|
MCR p15, 0, <Rd>, c7, c5, 4 | SBZ | Flush Prefetch Buffer[1]. |
MCR p15, 0, <Rd>, c7, c5, 6 | SBZ | Flush Entire Branch Target Cache[2]. |
MCR p15, 0, <Rd>, c7, c5, 7 | MVA[3] | Flush Branch Target Cache Entry, using MVA. |
[1] This operation is accessible in both User and privileged modes of operation. The other operations are normally only accessible in privileged mode, but see footnote b. [2] When in debug state, this operation is accessible in both privileged and User modes of operation. [3] As explained in MVA format, the range of MVA bits used in this function is different to the range of bits used in other functions that have MVA data. | ||
For the Flush Branch Target Cache Entry operation, the MVA does not have to be cache line aligned. See MVA format for details of the MVA format needed for the c7 entry for this operation.
Flushing the prefetch buffer has the effect that all instructions occurring in program order after this instruction are fetched from the memory system after the execution of this instruction, including the level one cache or TCM. This operation is useful for ensuring the correct execution of self-modifying code. See Explicit Memory Barriers on page 6-31.
The purpose of the Data Synchronization Barrier operation is to ensure that all outstanding explicit memory transactions complete before any following instructions begin. This ensures that data in memory is up-to-date before the processor executes any more instructions.
Historically, this operation has been referred to as Drain Write Buffer or Data Write Barrier (DWB). From ARMv6, these names, and the use of DWB, are deprecated in favor of the new Data Synchronization Barrier name (DSB). DSB better reflects the functionality provided in ARMv6; it is architecturally defined to include all cache, TLB and branch prediction maintenance operations as well as explicit memory operations.
The Data Synchronization Barrier operation is:
accessed through CP15 c7
a 32-bit write-only operation
accessible in both User and privileged modes.
This operation acts as an explicit memory barrier. The instruction completes when all explicit memory transactions occurring in program order before this instruction are completed. No instructions occurring in program order after this instruction are executed until this instruction completes. Therefore, no explicit memory transactions occurring in program order after this instruction are started until this instruction completes. See Explicit Memory Barriers on page 6-31.
It can be used instead of Strongly Ordered memory when the timing of specific stores to the memory system has to be controlled. For example, when a store to an interrupt acknowledge location must be completed before interrupts are enabled.
The Data Synchronization Barrier operation can be executed in both privileged and User modes of operation.
Table 3.83 shows the results of attempted accesses to the Data Synchronization Barrier operation for each mode.
Table 3.83. Results of accesses to the Data Synchronization Barrier operation
| Privileged read | Privileged write | User read | User write |
|---|---|---|---|
| Undefined exception | Operation executes | Undefined exception | Operation executes |
To use the Data Synchronization Barrier operation you write CP15 with:
<Rd> SBZ
Opcode_1 set to 0
CRn set to c7
CRm set to c10
Opcode_2 set to 4.
For example:
MCR p15,0,<Rd>,c7,c10,4 ; Data Synchronization Barrier operation
For more information, see Explicit Memory Barriers on page 6-31.
The W bit that normally enables the Write Buffer is not implemented in ARM1136JF-S processors, see c1, Control Register.
The purpose of the Data Memory Barrier operation is to ensure that all outstanding explicit memory transactions complete before any following explicit memory transactions begin. This ensures that data in memory is up-to-date before any memory transaction that depends on it.
The Data Memory Barrier operation is:
accessed through CP15 c7
a 32-bit write-only operation
accessible in both User and privileged modes.
Table 3.84 shows the results of attempted accesses to the Data Memory Barrier operation for each mode.
Table 3.84. Results of accesses to the Data Memory Barrier operation
| Privileged read | Privileged write | User read | User write |
|---|---|---|---|
| Undefined exception | Operation executes | Undefined exception | Operation executes |
To use the Data Memory Barrier operation you write CP15 with:
<Rd> SBZ
Opcode_1 set to 0
CRn set to c7
CRm set to c10
Opcode_2 set to 5.
For example:
MCR p15,0,<Rd>,c7,c10,5 ; Data Memory Barrier operation
For more information, see Explicit Memory Barriers on page 6-31.
The purpose of the Wait For Interrupt operation is to put the processor in to a low power state, see Standby mode.
The Wait For Interrupt operation is:
accessed through CP15 c7
a 32-bit write only operation
accessible in privileged mode only.
Table 3.85 shows the results of attempted accesses to the Wait For Interrupt operation for each mode.
Table 3.85. Results of accesses to the Wait For Interrupt operation
| Privileged read | Privileged write | User read or write |
|---|---|---|
| Undefined exception | Operation executes | Undefined exception |
To access the Wait For Interrupt operation you write CP15 with:
<Rd> SBZ
Opcode_1 set to 0
CRn set to c7
CRm set to c0
Opcode_2 set to 4.
For example:
MCR p15,0,<Rd>,c7,c0,4 ; Wait For Interrupt
This puts the processor into a low-power state and stops it
executing following instructions until an interrupt, an imprecise
external abort, or a debug request occurs, regardless of whether
the interrupts or external imprecise aborts are disabled by the masks
in the CPSR. When an interrupt does occur, the MCR instruction completes.
If interrupts are enabled, the IRQ or FIQ handler is entered as
normal. The return link in r14_irq or r14_fiq contains the address
of the MCR instruction plus 8, so that the normal instruction used
for interrupt return (SUBS PC,R14,#4) returns
to the instruction following the MCR.
The use of MCRR instructions for block transfer operations is described in Invalidate, Clean and Prefetch cache operations for address ranges. CP15 register c7 includes two additional operations that provide control of MCRR block transfer operations:
the read-only Read Block Transfer Register enables you to find out whether a block transfer operation is in progress
the write-only Stop Prefetch Range operation stops any prefetch range operation that is in progress.
Table 3.86 shows these CP15 register c7 operations.
Table 3.86. CP15 Register c7 block transfer control MCR/MRC operations
Function | Data | Instruction |
|---|---|---|
| Read Block Transfer Status Register[1] | Data |
|
Stop Prefetch Range[1] | SBZ |
|
[1] These operations are accessible in both User and privileged modes of operation (see Accesses to CP15 c7 operations). | ||
The purpose of the Block Transfer Status Register is to show whether a CP15 c7 block transfer operation is active.
The Block Transfer Status Register is:
in CP15 c7
a 32 bit read-only register
accessible in User and privileged modes.
Figure 3.42 shows the arrangement of bits in the register.
Table 3.87 shows the bit functions of the Block Transfer Status Register.
Table 3.87. Block Transfer Status Register bit functions
Bit range | Field name | Function |
|---|---|---|
[31:1] | - | RAZ |
| [0] | R | The R bit indicates if there is a block prefetch operation in progress. 0 indicates that no block prefetch operation is in progress. This is the reset value. 1 indicates that a block prefetch operation is in progress. |
Table 3.88 shows the results of attempted accesses to the Block Transfer Status Register for each mode.
Table 3.88. Results of accesses to the Block Transfer Status Register
| Privileged read | Privileged write | User read | User write |
|---|---|---|---|
| Data read | Undefined exception | Data read | Undefined exception |
To access the Block Transfer Status Register you read CP15 with:
Opcode_1 set to 0
CRn set to c7
CRm set to c12
Opcode_2 set to 4.
For example:
MRC p15,0,<Rd>,c7,c12,4 ; Read Block Transfer Status Register
Table 3.89 shows the results of attempted accesses to the Stop Prefetch Range operation for each mode.
Table 3.89. Results of accesses to the Stop Prefetch Range operation
| Privileged read | Privileged write | User read | User write |
|---|---|---|---|
| Undefined exception | Operation executes | Undefined exception | Operation executes |
To access the Stop Prefetch Range operation you write CP15 with:
<Rd> SBZ
Opcode_1 set to 0
CRn set to c7
CRm set to c12
Opcode_2 set to 5.
For example:
MCR p15,0,<Rd>,c7,c12,5 ; Stop Prefetch Range
| Copyright © 2002-2005 ARM Limited. All rights reserved. | ARM DDI 0211H |
| Non-Confidential | |
| PDF version | |
| Home > System Control Coprocessor > System control processor register descriptions > c7, Cache Operations Register |