ARM1136JF-S™ and ARM1136J-S™ Technical Reference Manual 6.13. MMU software-accessible registers

6.13. MMU software-accessible registers

The MMU is controlled by the system control coprocessor (CP15) registers, shown in Table 6.17, in conjunction with page table descriptors stored in memory.

You can access all the registers with instructions of the form:

MRC p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2>

MCR p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2>

Where CRn is the system control coprocessor register. Unless specified otherwise, CRm and Opcode_2 Should Be Zero.

Table 6.17. CP15 register functions

Register	Reference to description
TLB Type Register	See c0, TLB Type Register
Control Register	See c1, Control Register
Translation Table Base Register 0	See c2, Translation Table Base Register 0, TTBR0
Translation Table Base Register 1	See c2, Translation Table Base Register 1, TTBR1
Translation Table Base Control Register	See c2, Translation Table Base Control Register, TTBCR
Domain Access Control Register	See c3, Domain Access Control Register
Data Fault Status Register (DFSR)	See c5, Data Fault Status Register, DFSR
Instruction Fault Status Register (IFSR)	See c5, Instruction Fault Status Register, IFSR
Fault Address Register (FAR)	See c6, Fault Address Register, FAR
Watchpoint Fault Address Register (WFAR)	See c6, Watchpoint Fault Address Register, WFAR
Cache Operations Register	See c7, Cache Operations Register
TLB Operations Register	See c8, TLB Operations Register (invalidate TLB operation)
TLB Lockdown Register	See c10, TLB Lockdown Register
Primary Region Remap Register	See Primary Region Remap Register (PRRR)
Normal Memory Remap Register	See Normal Memory Remap Register (NMRR)
FCSE PID Register	See c13, FCSE PID Register
ContextID Register	See c13, Context ID Register
User Read/Write Thread and Process ID Register	See c13, Thread and process ID registers
User Read-only Thread and Process ID Register	See c13, Thread and process ID registers
Privileged Only Thread and Process ID Register	See c13, Thread and process ID registers

Note

All the CP15 MMU registers, except CP15 c7 and CP15 c8, contain state that you read using MRC instructions and written to using MCR instructions. Registers c5 and c6 are also written by the MMU. Reading CP15 c7 and c8 is Unpredictable. See the register descriptions for more information.

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