ARM1136JF-S™ and ARM1136J-S™ Technical Reference ManualRevision: r1p1
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3.3.1. c0, Main ID Register

The purpose of the Main ID Register is to return the device ID code that contains information about the processor.

The Main ID Register is:

Note

Before the r1p0 release, this register was called the ID Code Register.

Figure 3.9 shows the arrangement of bits in the register.

Figure 3.9. Main ID Register format

The contents of the Main ID Register depend on the specific implementation. Table 3.4 lists the bit functions of the Main ID Register.

Table 3.4. Main ID Register field descriptions

Bit rangeField name

Function

Value

[31:24]

Implementor

Indicates the implementor, ARM Limited.

0x41

[23:20]Variant numberImplementation-defined.

0x1[1]

[19:16]

Architecture

ARMv6

0x7

[15:4]

Primary part number

Implementation-defined.

Part number for ARM1136JF-S and ARM1136J-S

0xB36

[3:0]

Revision number

Implementation-defined. Revision number

0x1[2]

[1] Value given is for the rev1 (r1p0 and r1p1) releases of the ARM1136JF-S processor. For rev0 releases, the Variant number is 0x0. For the r0p2 release the Revision number is 0x2.

[2] Value given is for the r1p1 release of the ARM1136JF-S processor:    for the r1p0 release the Revision number is 0x0,    for the r0p2 release the Revision number is 0x2.

Note

If the processor encounters an Opcode_2 value corresponding to an unimplemented or reserved ID register with CRm = c0 and Opcode_1 = 0, the system control coprocessor returns the value of the Main ID Register.

Table 3.5 shows the results of attempted accesses to the Main ID Register for each mode.

Table 3.5. Results of accesses to the Main ID Register

Privileged readPrivileged writeUser read or write
Data readUndefined exceptionUndefined exception

Accessing the Main ID Register

To access the Main ID Register you read CP15 with:

  • Opcode_1 set to 0

  • CRn set to c0

  • CRm set to c0

  • Opcode_2 set to 0.

For example:

MRC p15,0,<Rd>,c0,c0,0               ; Read Main ID Register

For more information about the processor features, see c0, Core feature ID registers.

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