ARM1136JF-S™ and ARM1136J-S™ Technical Reference Manual 3.3.2. c0, Cache Type Register

3.3.2. c0, Cache Type Register

The purpose of the Cache Type Register is to provide information about the size and architecture of the caches. This enables the operating system to establish how to perform such operations as cache cleaning and lockdown. All ARMv4T and later cached processors contain this register, enabling RTOS vendors to produce future-proof versions of their operating systems.

The Cache Type Register is:

in CP15 c0
a 32-bit read only register
accessible in privileged mode only.

Figure 3.10 shows the arrangement of bits in the register.

Figure 3.10. Cache Type Register format

Table 3.6 lists the bit functions of the Cache Type Register.

Table 3.6. Cache Type Register field descriptions

Bits	Field name	Description
[31:29]	-	Always 0.
[28:25]	Ctype	Specifies if the cache supports lockdown or not, and how it is cleaned. See Table 3.7. For ARM1136JF-S processor Ctype = b1110.
[24]	S bit	Specifies whether the cache is a Unified Cache (S=0), or separate instruction and data caches (S=1). For ARM1136JF-S processors S = 1.
[23:12]	Dsize	Specifies the size, line length, and associativity of the Data Cache. See Figure 3.11 for the format of this field.
[11:0]	Isize	Specifies the size, line length, and associativity of the Instruction Cache. See Figure 3.11 for the format of this field.

Table 3.7 shows the encoding of the Ctype field for ARM1136JF-S processors.

Table 3.7. Ctype field encoding

Value	Method	Cache cleaning	Cache lockdown
b1110	Write-back	Register 7 operations	Format C

Figure 3.11 shows how the Dsize and Isize fields in the Cache Type Register have the same format.

Figure 3.11. Dsize and Isize field format

Table 3.8 shows a summary of Dsize and Isize fields shown in Figure 3.11.

Table 3.8. Dsize and Isize field summary

Field	Description
P bit	The P bit indicates if there is a restriction on page allocation for bits [13:12] of the Virtual Address: 0 = no restriction 1 = restriction applies to bits [13:12] of the Virtual Address. For ARM1136JF-S processors, the P bit is set if the cache size is greater than 16KB. For more details see Restrictions on page table mappings (page coloring).
Size	The Size field determines the cache size in conjunction with the M bit.
Assoc	The Assoc field determines the cache associativity in conjunction with the M bit. For ARM1136JF-S processor Ctype = b010.
M bit	The multiplier bit. Determines the cache size and cache associativity values in conjunction with the Size and Assoc fields. In the ARM1136JF-S processor the M bit is set to 0 for the Data and Instruction Caches.
Len	The Len field determines the line length of the cache. For ARM1136JF-S processor Len = b10.

The size of the cache is determined by the Size field and the M bit. The M bit is 0 for the Data and Instruction Caches. Bits [20:18] for the Data Cache and bits [8:6] for the Instruction Cache are the Size fields. Table 3.9 shows the cache size encoding.

Table 3.9. Cache size encoding (M=0)

Size field	Cache size
b000	0.5KB
b001	1KB
b010	2KB
b011	4KB
b100	8KB
b101	16KB
b110	32KB
b111	64KB

The associativity of the cache is determined by the Assoc field and the M bit. The M bit is 0 for the Data and Instruction Caches. Bits [17:15] for the Data Cache and bits [5:3] for the Instruction Cache are the Assoc field. Table 3.10 shows the cache associativity encoding.

Table 3.10. Cache associativity encoding (M=0)

Assoc field	Associativity
b000	Reserved
b001	Reserved
b010	4-way
b011	Reserved
b100
b101
b110
b111

The line length of the cache is determined by the Len field. Bits [13:12] for the Data Cache and bits [1:0] for the Instruction Cache are the Len field. Table 3.11 shows the line length encoding.

Table 3.11. Line length encoding

Len field	Cache line length
b00	Reserved
b01	Reserved
b10	8 words (32 bytes)
b11	Reserved

Accessing the Cache Type Register

Table 3.12 shows the results of attempted accesses to the Cache Type Register for each mode.

Table 3.12. Results of accesses to the Cache Type Register 0

Privileged read	Privileged write	User read or write
Data read	Undefined exception	Undefined exception

To access the Cache Type Register you read CP15 with:

Opcode_1 set to 0
CRn set to c0
CRm set to c0
Opcode_2 set to 1.

For example:

MRC p15,0,<Rd>,c0,c0,1               ; returns cache details

Cache Type Register read example

Table 3.13 shows the Cache Type Register values for an ARM1136JF-S processor with the following configuration:

separate instruction and data caches
cache size = 16KB
associativity = 4-way
line length = eight words
caches use write-back, CP15 c7 for cache cleaning, and Format C for cache lockdown.

Table 3.13. Example Cache Type Register format

Function		Register bits	Value
Reserved		[31:29]	b000
Ctype		[28:25]	b1110
S		[24]	b1 = Harvard cache
Dsize	P	[23]	b0
	Reserved	[22, 21]	b00
	Size	[20:18]	b101 = 16KB
	Assoc	[17:15]	b010 = 4-way
	M	[14]	b0
	Len	[13:12]	b10 = 8 words per line (32 bytes)
Isize	P	[11]	b0
	Reserved	[10:9]	b00
	Size	[8:6]	b101 = 16KB
	Assoc	[5:3]	b010 = 4-way
	M	[2]	b0
	Len	[1:0]	b10 = 8 words per line (32 bytes)

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