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8.5.10. Noncachable LDM7

The values of HTRANSR, HADDRR, HBURSTR, HSIZER, and HBSTRBR for Noncachable LDM7s are shown in Table 8.61 to Table 8.65.

Table 8.61. LDM7 from word 0, Strongly Ordered or Device memory

HTRANSRHADDRRHBURSTRHSIZERHBSTRBR
Nseq0x00Incr32-bitb00001111
Seq0x04b11110000
0x08b00001111
0x0Cb11110000
0x10b00001111
0x14b11110000
0x18b00001111

Table 8.62. LDM7 from word 0, Noncachable memory or cache disabled

HTRANSRHADDRRHBURSTRHSIZERHBSTRBR
Nseq0x00Incr464-bitb11111111[1]
Seq0x08
0x10
0x18b00001111[1]

[1] Denotes that HUNALIGNR is asserted for that transfer. This is only for ARMv6 unaligned loads and loads to normal memory, where reading more data than is necessary is possible.

Table 8.63. LDM7 from word 1, Strongly Ordered or Device memory

HTRANSRHADDRRHBURSTRHSIZERHBSTRBR
Nseq0x04Incr32-bitb11110000
Seq0x08b00001111
0x0Cb11110000
0x10b00001111
0x14b11110000
0x18b00001111
0x1Cb11110000

Table 8.64. LDM7 from word 1, Noncachable memory or cache disabled

HTRANSRHADDRRHBURSTRHSIZERHBSTRBR
Nseq0x00Incr464-bitb11110000[1]
Seq0x08b11111111
0x10
0x18

[1] Denotes that HUNALIGNR is asserted for that transfer. This is only for ARMv6 unaligned loads and loads to normal memory, where reading more data than is necessary is possible.

Table 8.65. LDM7 from word 2, 3, 4, 5, 6, or 7

Address[4:0]Operations
0x08 (word 2)LDM6 from 0x08 + LDR from 0x00
0x0C (word 3)LDM5 from 0x0C + LDM2 from 0x00
0x10 (word 4)LDM4 from 0x10 + LDM3 from 0x00
0x14 (word 5)LDM3 from 0x14 + LDM4 from 0x00
0x18 (word 6)LDM2 from 0x18 + LDM5 from 0x00
0x1C (word 7)LDR from 0x1C + LDM6 from 0x00
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