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The various memory types defined in this section have restrictions in the memory orderings that are allowed.
The order of any two explicit architectural memory accesses where one or more are to memory marked as Non-Shared must obey the ordering requirements shown in Table 6.11.
Table 6.11 shows the memory ordering between two explicit accesses A1 and A2, where A1 occurs before A2 in program order. The symbols used in the table are as follows:
Accesses must occur strictly in program order. That is, A1 must occur strictly before A2. It must be impossible to tell otherwise from observation of the read/write values and side effects caused by the memory accesses.
Accesses can occur in any order, provided that the requirements of uniprocessor semantics are met, for example respecting dependencies between instructions within a single processor.
Table 6.11. Memory ordering restrictions
| A2 | |||||||||
|---|---|---|---|---|---|---|---|---|---|
Normal read | Device read, NS[1] | Device read, S[1] | Strongly Ordered read | Normal write | Device write, NS[1] | Device write, S[1] | Strongly Ordered write | ||
| A1 | Normal read | ? | ? | ? | < | ?[2] | ? | ? | < |
Device read, NS[1] | ? | < | ? | < | ? | < | ? | < | |
Device read, S[1] | ? | ? | < | < | ? | ? | < | < | |
Strongly Ordered read | < | < | < | < | < | < | < | < | |
Normal write | ? | ? | ? | < | ?[2] | ? | ? | < | |
Device write, NS[1] | ? | < | ? | < | ? | < | ? | < | |
Device write, S[1] | ? | ? | < | < | ? | ? | < | < | |
Strongly Ordered write | < | < | < | < | < | < | < | < | |
[1] NS = Non-Shared, S = Shared. [2] ARM1136JF-S processor orders the normal read ahead of normal write. | |||||||||
There are no ordering requirements for implicit accesses to any type of memory.
The program order of instruction execution is defined as the order of the instructions in the control flow trace. Two explicit memory accesses in an execution can either be:
Denoted by <. If the accesses are Ordered, then they must occur strictly in order.
Denoted by <=. If the accesses are Weakly Ordered, then they must occur in order or simultaneously.
The rules for determining this for two accesses A1 and A2 are:
If A1 and A2 are generated by two different instructions, then:
A1 < A2 if the instruction that generates A1 occurs before the instruction that generates A2 in program order.
A2 < A1 if the instruction that generates A2 occurs before the instruction that generates A1 in program order.
If A1 and A2 are generated by the same instruction, then:
If A1 and A2 are the load and store generated by a SWP or SWPB instruction, then:
A1 < A2 if A1 is the load and A2 is the store
A2 < A1 if A2 is the load and A1 is the store.
If A1 and A2 are two word loads generated by an LDC, LDRD, or LDM instruction, or two word stores generated by an STC, STRD, or STM instruction, but excluding LDM or STM instructions whose register list includes the PC, then:
A1 <= A2 if the address of A1 is less than the address of A2
A2 <= A1 if the address of A2 is less than the address of A1.
If A1 and A2 are two word loads generated by an LDM instruction whose register list includes the PC or two word stores generated by an STM instruction whose register list includes the PC, then the program order of the memory operations is not defined.
Multiple load and store instructions (such as LDM, LDRD, STM, and STRD) generate multiple word accesses, each being a separate access to determine ordering.
| Copyright © 2002-2006 ARM Limited. All rights reserved. | ARM DDI 0211I |
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