[31:30]

-

Reserved. This field is UNP/RAZ when read. Write as the existing value.

Access Flag Enable. This bit controls the generation of Access Flag (AF) faults by AP[0].

0 = Generation of AF faults by AP[0] is disabled. Normal ARMv6 behavior. Reset value.

1 = Generation of AF faults by AP[0] is enabled.

The AFE bit is only defined from the rev1 (r1p0) release of the ARM1136JF-S processor. This bit is reserved in earlier releases (UNP/RAZ when read, write as the existing value).

TEX Remap enable. This bit controls the TEX remap functionality in the MMU.

0 = TEX remap disabled. Normal ARMv6 behavior. Reset value.

1 = TEX remap enabled. TEX[2:1] become page table bits for OS.

The TRE bit is only defined from the rev1 (r1p0) release of the ARM1136JF-S processor. This bit is reserved in earlier releases (UNP /RAZ when read, write as the existing value).

[27:26]

-

Reserved. This field is UNP/RAZ when read. Write as the existing value.

This bit determines the setting of the CPSR E bit on taking an exception:

0 = CPSR E bit is set to 0 on taking an exception

1 = CPSR E bit is set to 1 on taking an exception.

The reset value of this bit depends on external signals, see Control Register reset value.

Configure vectored interrupt. Enables the VIC interface to determine the interrupt vectors:

0 = Interrupt vectors are fixed. See the description of the V bit (bit 13)

1 = Interrupt vectors are defined by the VIC interface.

Configure extended page table configuration. This bit configures the hardware page translation mechanism:

0 = Subpage AP bits enabled

1 = Subpage AP bits disabled (ARMv6 mode).

Enables unaligned data access operations, including support for mixed little-endian and big-endian operation. The A bit has priority over the U bit.

0 = Unaligned data access support disabled, reset value. The processor treats unaligned loads as rotated aligned data accesses.

1 = Unaligned data access support enabled. The processor permits unaligned loads and stores and support for mixed endian data is enabled.

The reset value of this bit depends on external signals, see Control Register reset value.

Configure fast interrupt configuration:

0 = All performance features enabled

1 = Low interrupt latency configuration enabled.

This bit enables low interrupt latency features, see Low interrupt latency configuration.

Reserved. This field is UNP/RAZ when read. Write as the existing value.

Global Instruction TCM enable/disable bit. This bit is used in ARM946 and ARM966 processors to enable the Instruction TCM. In ARMv6, the TCM blocks have individual enables that apply to each block. As a result, this bit is now redundant.

This bit Should Be One on writes, and returns one on reads.

See c9, Instruction TCM Region Register for a description of the ARM1136JF-S TCM enables.

Reserved. This field is UNP/RAZ when read. Write as the existing value.

Global Data TCM enable/disable bit. This bit is used in ARM946 and ARM966 processors to enable the Data TCM. In ARMv6, the TCM blocks have individual enables that apply to each block. As a result, this bit is now redundant.

This bit Should Be One on writes, and returns one on reads.

See c9, Instruction TCM Region Register for a description of the ARM1136JF-S TCM enables.

[15]

L4 bit

Configure if load instructions to PC set the T bit:

0 = Loads to PC set the T bit

1 = Loads to PC do not set the T bit (ARMv4 behavior).

For more details see the ARM Architecture Reference Manual.

[14]

RR bit

Replacement strategy for the instruction and data caches:

0 = Normal replacement strategy (Random replacement)

1 = Predictable replacement strategy (Round-Robin replacement).

V bit

Location of exception vectors:

0 = Normal exception vectors selected, address range = 0x00000000-0x0000001C

1 = High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C.

The reset value of this bit depends on the external VINITHI signal, see Control Register reset value.

I bit

Level one Instruction Cache enable/disable:

0 = Instruction Cache disabled

1 = Instruction Cache enabled.

Z bit

Program flow prediction:

0 = Program flow prediction disabled

1 = Program flow prediction enabled.

Program flow prediction includes static and dynamic branch prediction and the return stack. This bit enables all three forms of program flow prediction. You can enable or disable each form individually, see c1, Auxiliary Control Register.

The meaning of this bit is Implementation-defined.

For ARM1136JF-S processors, this bit Should Be Zero on writes and Reads As Zero on reads.

R bit

ROM protection. This bit modifies the ROM protection system:

0 = ROM protection disabled

1 = ROM protection enabled.

Modifying the R bit does not affect the access permissions of entries already in the TLB. See MMU software-accessible registers.

S bit

System protection. This bit modifies the MMU protection system:

0 = MMU protection disabled

1 = MMU protection enabled.

Modifying the S bit does not affect the access permissions of entries already in the TLB.

B bit

Determines operation as little-endian or big-endian word invariant memory system and the names of the low four-byte addresses within a 32-bit word:

0 = Little-endian memory system

1 = Big-endian word-invariant memory system.

The reset value of this bit depends on external signals, see Control Register reset value.

-

When read returns one and when written Should Be One.

C bit

Level one Data Cache enable/disable:

0 = Data cache disabled

1 = Data cache enabled.

A bit

Strict data address alignment fault enable/disable:

0 = Strict alignment fault checking disabled

1 = Strict alignment fault checking enabled.

The A bit setting takes priority over the U bit. The Data Abort trap is taken if strict alignment is enabled and the data access is not aligned to the width of the accessed data item.

M bit

MMU enable/disable:

0 = MMU disabled

1 = MMU enabled.