ARM1136JF-S™ and ARM1136J-S™ Technical Reference Manual 3.3.3. c0, TCM Status Register

The purpose of the TCM Status Register is to inform the system about the number of Instruction and Data TCMs available in the processor.

The ARM1136JF-S processor implements only one Instruction TCM and one Data TCM.

The TCM Status Register is:

Figure 3.12 shows the arrangement of bits in the register.

Figure 3.12. TCM Status Register format

Table 3.14 lists the bit functions of the TCM Status Register.

Table 3.14. TCM Status Register field descriptions

Bits	Field name	Description
[31:29]	-	Always 0.
[28:19]	-	SBZ/UNP.
[18:16]	DTCM	Specifies the number of Data TCMs implemented. For ARM1136JF-S processors this value is 1.
[15:3]	-	SBZ/UNP.
[11:0]	ITCM	Specifies the number of Instruction TCMs implemented. For ARM1136JF-S processors this value is 1.

Table 3.15 shows the results of attempted accesses to the TCM Status Register for each mode.

Table 3.15. Results of accesses to the TCM Status Register

Privileged read	Privileged write	User read or write
Data read	Undefined exception	Undefined exception

To access the TCM Status Register you read CP15 c0 with:

For example:

MRC p15,0,<Rd>,c0,c0,2                 ; returns TCM status register

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