ARM1136JF-S™ and ARM1136J-S™ Technical Reference Manual 3.3.14. c5, Instruction Fault Status Register, IFSR

3.3.14. c5, Instruction Fault Status Register, IFSR

The purpose of the Instruction Fault Status Register (IFSR) is to hold the source of the last instruction fault. The IFSR indicates the type of access being attempted when an abort occurred.

The Instruction Fault Status Register is:

in CP15 c5
a 32-bit read/write register
accessible in privileged mode only.

Figure 3.34 shows the arrangement of bits in the register.

Figure 3.34. Instruction Fault Status Register format

Table 3.64 shows the bit functions of the Instruction Fault Status Register.

Table 3.64. Instruction Fault Status Register bits

Bit range	Field name	Meaning
[31:11]	-	UNP/SBZ.
[10]	-	Always 0.
[9:4]	-	UNP/SBZ.
[3:0]	Status	Type of fault generated. See Table 3.65 for a list of the fault encodings, and Fault status and address for full details of Domain and FAR validity.

The fault status field bit encodings are shown in Table 3.65.

Table 3.65. IFSR fault status encoding

Status[3:0]^[1]	Fault source
b0000	No function, reset value
b0001	Alignment fault
b0010	Debug event fault
b0011	Access Flag fault on Section
b0100	No function^[2]
b0101	Translation fault on Section
b0110	Access Flag fault on Page
b0111	Translation fault on Page
b1000	Precise External Abort
b1001	Domain fault on Section
b1010	No function
b1011	Domain fault on Page
b1100	External abort on translation, first level
b1101	Permission fault on Section
b1110	External abort on translation, second level
b1111	Permission fault on Page
^[1]Bits[3:0] of the IFSR register. ^[2]On the DFST, the corresponding encoding (0b00100) indicates a cache maintenance operation fault. These faults cannot occur on the instruction side.

Accessing the Instruction Fault Status Register

Table 3.66 shows the results of attempted accesses to the Instruction Fault Status Register for each mode.

Table 3.66. Results of accesses to the Instruction Fault Status Register

Privileged read	Privileged write	User read or write
Data read	Data write	Undefined exception

To access the Instruction Fault Status Register you read or write CP15 with:

Opcode_1 set to 0
CRn set to c5
CRm set to c0
Opcode_2 set to 1.

For example:

MRC p15, 0, <Rd>, c5, c0, 1            ; Read Instruction Fault Status Register

MCR p15, 0, <Rd>, c5, c0, 1            ; Write Instruction Fault Status Register

Reading CP15 c5 with the Opcode_2 field set to 1 returns the value of the IFSR.

Writing CP15 c5 with the Opcode_2 field set to 1 sets the IFSR to the value of the data written. This is useful for a debugger to restore the value of the IFSR. Bits [31:4] Should Be Zero.

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