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| Home > System Control Coprocessor > System control processor register descriptions > c2, Translation Table Base Register 0, TTBR0 |
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The purpose of the Translation Table Base Register 0 is to hold the physical address of the first-level translation table.
You use Translation Table Base Register 0 for process-specific addresses, where each process maintains a separate first-level page table. On a context switch you must modify both Translation Table Base Register 0 and the Translation Table Base Control Register, if appropriate.
The Translation Table Base Register 0 is:
in CP15 c2
a 32 bit read/write register
accessible in privileged mode only.
Figure 3.29 shows the bit functions of the register.
Table 3.52 lists the bit functions of the Translation Table Base Register 0.
Table 3.52. Translation Table Base Register 0 field descriptions
| Bits | Name | Function |
|---|---|---|
| [31:(14-N)][1] | Translation table base 0 | Pointer to the level one translation table. |
| [(13-N):5][1] | - | UNP/SBZ. |
| [4:3] | RGN | Outer cachable attributes for page table walking: b00 = Outer Noncachable b01 = Outer Cachable Write-Back cached, Write Allocate b10 = Outer Cachable Write-Through, No Allocate on Write b11 = Outer Cachable Write-Back, No Allocate on Write. |
| [2] | P | If ECC is supported, indicates to the memory controller whether it is enabled (P=1) or disabled (P=0). For ARM1136JF-S processors this bit Should Be Zero. |
| [1] | S | Indicates whether the page table walk is to Shared or Non-Shared memory. 0 = Non-Shared. This is the reset value. 1 = Shared. |
| [0] | C | Indicates whether the page table walk is Inner Cachable or Inner Noncachable. 0 = Inner noncachable. This is the reset value. 1 = Inner cachable. |
[1] The value of N is defined in the Translation Table Base Control Register, see c2, Translation Table Base Control Register, TTBCR. | ||
Table 3.53 shows the results of attempted accesses to the Translation Table Base Register 0 for each mode.
Table 3.53. Results of accesses to the Translation Table Base Register 0
| Privileged read | Privileged write | User read or write |
|---|---|---|
| Data read | Data write | Undefined exception |
To access the Translation Table Base Register 0 you read or write CP15 with:
Opcode_1 set to 0
CRn set to c2
CRm set to c0
Opcode_2 set to 0.
For example:
MRC p15, 0, <Rd>, c2, c0, 0 ; Read Translation Table Base Register 0
MCR p15, 0, <Rd>, c2, c0, 0 ; Write Translation Table Base Register 0
The ARM1136JF-S processor cannot perform a page table walk from level one cache. Therefore, to ensure coherency, when C = 1 you must do one of:
store the page tables in Inner Write-Through memory
if in Inner Write-Back memory, clean the appropriate cache entries after modification to ensure that they are seen by the hardware page table walking mechanism.
| Copyright © 2002-2006 ARM Limited. All rights reserved. | ARM DDI 0211I |
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