ARM1136JF-S™ and ARM1136J-S™ Technical Reference Manual 3.3.46. Registers for MMU debug operations

3.3.46. Registers for MMU debug operations

The arrangement of the registers for MMU debug operations is shown in Figure 3.69. The registers are described in the following sections:

c15, Instruction MicroTLB and Data MicroTLB Index Registers

The purpose of the MicroTLB Index Registers is to provide access to the Instruction and Data MicroTLB entries.

The MicroTLB Index Registers are:

in CP15 c15
two 32 bit read/write registers
- the Instruction MicroTLB Index Register
- the Data MicroTLB Index Register
accessible in privileged mode only.

Figure 3.70 shows the arrangement of bits in the registers.

Figure 3.70. MicroTLB index format

Table 3.157 shows the bit functions of the MicroTLB Index Registers.

Table 3.157. MicroTLB Index Registers bit functions

Bit range	Field name	Function
[31:4]		SBZ/UNP.
[3:0]	Index	Indicates which entry in the MicroTLB is accessed. Allowed values are b‘0000 to b‘1010, decimal 0 to 10.

Bit range

Field name

Function

[31:4]

SBZ/UNP.

[3:0]

Index

Indicates which entry in the MicroTLB is accessed.

Allowed values are b‘0000 to b‘1010, decimal 0 to 10.

Note

MicroTLB index values greater than 10 do not access any MicroTLB entry.

Accessing the MicroTLB Index Registers

Table 3.158 shows the results of attempted accesses to the Instruction MicroTLB and Data MicroTLB Index Registers for each mode.

Table 3.158. Results of accesses to the Instruction MicroTLB and Data MicroTLB Index Registers

Privileged read	Privileged write	User read or write
Data read	Data write	Undefined exception

To access the MicroTLB Index Registers you read or write CP15 with:

Opcode_1 set to 5
CRn set to c15
CRm set to c4
Opcode_2 set to:
- 0 to access the Data MicroTLB Index Register
- 1 to access the Instruction MicroTLB Index Register.

For example:

MRC p15, 5, <Rd>, c15, c4, 0         ; Read Data MicroTLB Index Register

MCR p15, 5, <Rd>, c15, c4, 0         ; Write Data MicroTLB Index Register

MRC p15, 5, <Rd>, c15, c4, 1         ; Read Instruction MicroTLB Index Register

MCR p15, 5, <Rd>, c15, c4, 1         ; Write Instruction MicroTLB Index Register

See MicroTLB debug for a description of using the MicroTLB Index Registers for debugging the MicroTLBs.

c15, Main TLB Entry Registers (Main TLB index)

The purpose of the Main Entry Registers is to provide access to main TLB read and write entries. There are separate registers for indexing main TLB entry reads and writes. The registers are also referred to as the Main TLB Index Registers.

The Main TLB Entry Registers are:

in CP15 c15
two 32 bit write-only registers
- the Read Main TLB Entry Register
- the Write Main TLB Entry Register
accessible in privileged mode only.

Figure 3.71 shows the arrangement of bits in the registers.

Figure 3.71. Main TLB Index format

Table 3.159 the bit functions of the Main TLB Entry Registers.

Table 3.159. Main TLB Entry Registers bit functions

Bit range	Name	Meaning
[31]	L	Lockable region. Indicates whether the index s to the lockable region or the set-associative region: 0 = Index s to the set-associative region 1 = Index s to the lockable region.
[30:6]	-	SBZ.
[5:0]	Index	Indicates which entry in the main TLB is accessed. The meaning of this field depends on the setting of the L bit: L = 0 Index[5] indicates which Way of the main TLB set-associative region is being accessed. Index[4:0] indexes the Set of the RAM. L = 1 Index[5:3] SBZ. Index[2:0] indicates which entry in the lockable region is being accessed.

Bit range

Name

Meaning

[31]

Lockable region. Indicates whether the index s to the lockable region or the set-associative region:

0 = Index s to the set-associative region

1 = Index s to the lockable region.

[30:6]

SBZ.

[5:0]

Index

Indicates which entry in the main TLB is accessed. The meaning of this field depends on the setting of the L bit:

L = 0

Index[5] indicates which Way of the main TLB set-associative region is being accessed.

Index[4:0] indexes the Set of the RAM.

L = 1

Index[5:3] SBZ.

Index[2:0] indicates which entry in the lockable region is being accessed.

Accessing the Main TLB Entry Registers

Table 3.160 shows the results of attempted accesses to the Main TLB Entry Registers for each mode.

Table 3.160. Results of accesses to the Main TLB Entry Registers

Privileged read	Privileged write	User read or write
Undefined exception	Data write	Undefined exception

To access the Main TLB Entry Registers you write CP15 with:

Opcode_1 set to 5
CRn set to c15
CRm set to c4
Opcode_2 set to:
- 2 to access the Read Main TLB Entry Register
- 4 to access the Write Main TLB Entry Register.

For example:

MCR p15, 5, <Rd>, c15, c4, 2          ; Write to Read Main TLB Entry Register

MCR p15, 5, <Rd>, c15, c4, 4          ; Write to Write Main TLB Entry Register

See Main TLB debug for a description of using the Main TLB Entry Registers for debugging the main TLBs.

c15, TLB VA Registers

The purpose of the TLB VA Registers is to provide access to TLB Virtual Address (VA) information. The registers enable you to:

Read VA information for the Data and Instruction MicroTLBs
Read or write VA information for the main TLB.

The TLB VA Registers are:

in CP15 c15
two 32 bit read-only registers and one 32 bit read/write register:
- the Data MicroTLB VA Register (read-only)
- the Instruction MicroTLB VA Register (read-only)
- the Main TLB VA Register (read/write)
accessible in privileged mode only.

Figure 3.72 shows the arrangement of bits in the registers.

Figure 3.72. TLB VA Registers format

Table 3.161 shows the bit functions of the TLB VA Registers.

Table 3.161. TLB VA Registers bit functions

Bit range	Name	Function
[31:10]	VPN	Virtual Page Number. Bits of the virtual page number that are not translated as part of the page table translation because the size of the tables are Unpredictable when read, and Should Be Zero when written^[1].
[9:0]	PROCESS	Memory space identifier that determines if the entry is a global mapping, or an ASID dependent entry. See Figure 3.73 for the format of this field.
^[1]MicroTLB PA Registers cannot be written; see Accessing the TLB VA Registers.

Bit range

Name

Function

[31:10]

VPN

Virtual Page Number.

Bits of the virtual page number that are not translated as part of the page table translation because the size of the tables are Unpredictable when read, and Should Be Zero when written^[1].

[9:0]

PROCESS

Memory space identifier that determines if the entry is a global mapping, or an ASID dependent entry. See Figure 3.73 for the format of this field.

^[1]MicroTLB PA Registers cannot be written; see Accessing the TLB VA Registers.

Figure 3.73 shows the format of the memory space identifier.

Figure 3.73. TLB VA Registers memory space identifier format

Accessing the TLB VA Registers

Table 3.162 shows the results of attempted accesses to the Data MicroTLB VA and Instruction MicroTLB VA Registers for each mode.

Table 3.162. Results of accesses to the Data MicroTLB VA and Instruction MicroTLB VA Registers

Privileged read	Privileged write	User read or write
Data read	Undefined exception	Undefined exception

Table 3.163 shows the results of attempted accesses to the Main TLB VA Register for each mode.

Table 3.163. Results of accesses to the Main TLB VA Register

Privileged read	Privileged write	User read or write
Data read	Data write	Undefined exception

To access the Data MicroTLB VA Register or the Instruction MicroTLB VA Register you read CP15 with:

Opcode_1 set to 5
CRn set to c15
CRm set to c5
Opcode_2 set to
- 0 to access the Data MicroTLB VA Register
- 1 to access the Instruction MicroTLB VA Register.

For example:

MRC p15, 5, <Rd>, c15, c5, 0            ; Read Data MicroTLB VA Register

MRC p15, 5, <Rd>, c15, c5, 1            ; Read Instruction MicroTLB VA Register

To access the Main TLB VA Register you read or write CP15 with:

Opcode_1 set to 5
CRn set to c15
CRm set to c5
Opcode_2 set to 2.

For example:

MRC p15, 5, <Rd>, c15, c5, 2            ; Read Main TLB VA Register

MCR p15, 5, <Rd>, c15, c5, 2            ; Write Main TLB VA Register

See MicroTLB debug for a description of using the MicroTLB VA Registers for debugging the MicroTLBs, and Main TLB debug for a description of using the Main TLB VA Register for debugging the main TLBs.

c15, TLB PA Registers

The purpose of the TLB PA Registers is to provide access to TLB Physical Address (PA) information. The registers enable you to:

Read VPA information for the Data and Instruction MicroTLBs
Read or write PA information for the main TLB.

The TLB PA Registers are:

in CP15 c15
two 32 bit read-only registers and one 32 bit read/write register:
- the Data MicroTLB PA Register (read-only)
- the Instruction MicroTLB PA Register (read-only)
- the Main TLB PA Register (read/write)
accessible in privileged mode only.

Figure 3.74 shows the arrangement of bits in the registers.

Figure 3.74. TLB PA Registers format

Table 3.164 describes the functions of the TLB PA Register bits.

Table 3.164. TLB PA Registers bit functions

Bit range	Name	Function
[31:10]	PPN	Physical Page Number. Bits of the physical page number that are not translated as part of the page table translation are Unpredictable when read and Should Be Zero when written^[1].
[9:6]	SZ	Region size. Table 3.165 shows the format of the SZ field. The region size that is contained in the MicroTLB might be smaller than specified in the page tables. The MicroTLB can split main TLB entries that cover regions which cover areas of memory contained in the TCM into smaller sizes. In addition, subpages are reported as separate pages in the MicroTLBs.
[5:4]	XRGN	Extended Region Type. Table 3.166 shows the region type bits used to determine the attributes for the memory region.
[3:1]	AP	Access Permissions. Table 3.167 shows the format of the AP field: for MicroTLB entries this field contains the access permissions for the subpage that is contained in that MicroTLB entry for main TLB entries, this register contains the access permission fields for the first subpage, or for the entire page/section if the page does not support subpages.
[0]	V	Valid bit. Indicates that this TLB entry is valid.
^[1]MicroTLB PA Registers cannot be written; see Accessing the TLB PA Registers.

Table 3.165 shows the encoding of the SZ field.

Table 3.165. TLB PA Registers SZ field encoding

SZ	Description
b1111	1KB subpage (used by MicroTLB only)
b1110	4KB page
b1100	16KB subpage (used by MicroTLB only)
b1000	64KB page
b0000	1MB section (or part of 16MB supersection for MicroTLB)
b0001	16M Supersection (used by main TLB only)
All other values	Reserved

Table 3.166 shows the encoding of the XRGN field.

Table 3.166. TLB PA Registers XRGN field encoding

XRGN	Description
b00	Outer Noncachable
b01	Outer WB, Allocate On Write
b10	Outer WT, No Allocate on Write
b11	Outer WB, No Allocate on Write

Table 3.167 shows the encoding of the AP field.

Table 3.167. TLB PA Registers AP field encoding

AP field	Supervisor permissions	User permissions	Description
b000	No access	No access	All accesses generate a permission fault
b001	Read/write	No access	Supervisor access only
b010	Read/write	Read-only	Writes in User mode generate permission faults
b011	Read/write	Read/write	Full access
b100	No access	No access	Domain fault encoded field
b101	Read-only	No access	Supervisor read-only
b110	Read-only	Read-only	Supervisor/User read-only
b111	-	-	Reserved

Accessing the TLB PA Registers

Table 3.168 shows the results of attempted accesses to the Data MicroTLB PA and Instruction MicroTLB PA Registers for each mode.

Table 3.168. Results of accesses to the Data MicroTLB PA and Instruction MicroTLB PA Registers

Privileged read	Privileged write	User read or write
Data read	Undefined exception	Undefined exception

Table 3.169 shows the results of attempted accesses to the Main TLB PA Register for each mode.

Table 3.169. Results of accesses to the Main TLB PA Register

Privileged read	Privileged write	User read or write
Data read	Data write	Undefined exception

To access the Data MicroTLB PA Register or the Instruction MicroTLB PA Register you read CP15 with:

Opcode_1 set to 5
CRn set to c15
CRm set to c6
Opcode_2 set to
- 0 to access the Data MicroTLB PA Register
- 1 to access the Instruction MicroTLB PA Register.

For example:

MRC p15, 5, <Rd>, c15, c6, 0            ; Read Data MicroTLB PA Register

MRC p15, 5, <Rd>, c15, c6, 1            ; Read Instruction MicroTLB PA Register

To access the Main TLB PA Register you read or write CP15 with:

Opcode_1 set to 5
CRn set to c15
CRm set to c6
Opcode_2 set to 2.

For example:

MRC p15, 5, <Rd>, c15, c6, 2            ; Read Main TLB PA Register

MCR p15, 5, <Rd>, c15, c6, 2            ; Write Main TLB PA Register

See MicroTLB debug for a description of using the MicroTLB PA Registers for debugging the MicroTLBs, and Main TLB debug for a description of using the Main TLB PA Register for debugging the main TLBs.

c15, TLB Attribute Registers

The purpose of the TLB Attribute Registers is to provide access to the TLB attributes. The registers enable you to:

Read attribute information for the Data and Instruction MicroTLBs
Read or write attribute information for the main TLB.

The TLB Attribute Registers are:

in CP15 c15
two 32 bit read-only registers and one 32 bit read/write register:
- the Data MicroTLB Attribute Register (read-only)
- the Instruction MicroTLB Attribute Register (read-only)
- the Main TLB PA Attribute Register (read/write)
accessible in privileged mode only.

Figure 3.75 shows the arrangement of bits in the Main TLB Attribute Register, and Figure 3.76 shows the arrangement of bits in the MicroTLB Attribute Registers.

Figure 3.75. Main TLB Attribute Register format

Figure 3.76. MicroTLB Attribute Registers format

Table 3.170 shows the bit functions of the TLB Attribute Registers.

Table 3.170. TLB Attribute Registers bit functions

Bit range	Name	Function
[31:30]	AP3	Main TLB Attributes register only. Subpage access permissions for the fourth subpage if the page or section supports subpages. Unpredictable on read and Should Be Zero on a write if the entry does not support subpages. The format for the permissions is shown as the upper subpage permissions in Table 3.171. This field is Unpredictable for reads from the MicroTLB.
[29:28]	AP2	Main TLB Attributes register only. Subpage access permissions for third subpage if the page or section supports subpages. Unpredictable on read and Should Be Zero on a write if the entry does not support subpages. The format for the permissions is shown as the upper subpage permissions in Table 3.171. This field is Unpredictable for reads from the MicroTLB.
[27:26]	AP1	Main TLB Attributes register only. Subpage access permissions for second subpage if the page or section supports subpages. Unpredictable on read and Should Be Zero on a write if the entry does not support subpages. The format for the permissions is shown as the upper subpage permissions in Table 3.171. This field is Unpredictable for reads from the MicroTLB.
[25]	SPV	Subpage Valid. Indicates that the page or section supports subpages. Pages that support subpages must be marked as Global. Attempting to use subpages with non-global pages has Unpredictable results: 0 = Subpages are not supported 1 = Subpages are supported. This field is 0 for reads from the MicroTLB.
[24:9]	-	Should Be Zero.
[8:5]	Domain	Domain number of the TLB entry.
[4]	XN	Execute Never attribute. This field is Unpredictable for a read from the Data MicroTLB Attribute Register.
[3:1]	RGN	Region type. Table 3.172 shows the format of the extended region field.
[0]	S	Shared attribute.

Table 3.171 shows the Upper subpage access permission field encodings.

Table 3.171. Upper subpage access permission field encoding

Upper subpage permissions AP[1:0]	CP15		Description
Upper subpage permissions AP[1:0]	S	R	Description
b00	0	0	All accesses generate a permission fault.
b00	1	0	Supervisor read-only. User no access.
b00	0	1	Supervisor or User read-only.
b00	1	1	Unpredictable.
b01	X	X	Supervisor access only.
b10	X	X	Supervisor full access. User read-only.
b11	X	X	Full access.

Table 3.172 shows the encoding of the RGN field.

Table 3.172. RGN field encoding

RGN	Description
b000	Noncachable
b001	Strongly Ordered
b010	Reserved
b011	Device
b100	Reserved
b101	Reserved
b110	Inner WT, No Allocate on Write
b111	Inner WB, No Allocate on Write

Table 3.168 shows the results of attempted accesses to the Data MicroTLB Attribute and Instruction MicroTLB Attribute Registers for each mode.

Table 3.173. Results of accesses to the Data MicroTLB Attribute and Instruction MicroTLB Attribute Registers

Privileged read	Privileged write	User read or write
Data read	Undefined exception	Undefined exception

Table 3.169 shows the results of attempted accesses to the Main TLB Attribute Register for each mode.

Table 3.174. Results of accesses to the Main TLB Attribute Register

Privileged read	Privileged write	User read or write
Data read	Data write	Undefined exception

To access the Data MicroTLB Attribute Register or the Instruction MicroTLB Attribute Register you read CP15 with:

Opcode_1 set to 5
CRn set to c15
CRm set to c7
Opcode_2 set to
- 0 to access the Data MicroTLB Attribute Register
- 1 to access the Instruction MicroTLB Attribute Register.

For example:

MRC p15, 5, <Rd>, c15, c7, 0      ; Read Data MicroTLB Attribute Register

MRC p15, 5, <Rd>, c15, c7, 1      ; Read Instruction MicroTLB Attribute Register

To access the Main TLB Attribute Register you read or write CP15 with:

Opcode_1 set to 5
CRn set to c15
CRm set to c7
Opcode_2 set to 2.

For example:

MRC p15, 5, <Rd>, c15, c7, 2            ; Read Main TLB Attribute Register

MCR p15, 5, <Rd>, c15, c7, 2            ; Write Main TLB Attribute Register

See MicroTLB debug for a description of using the MicroTLB Attribute Registers for debugging the MicroTLBs, and Main TLB debug for a description of using the Main TLB Attribute Register for debugging the main TLBs.

c15, TLB Debug Control Register

The purpose of the TLB Debug Control Register is to provide control of TLB operations for debug purposes.

The TLB Debug Control Register is:

in CP15 c15
a 32 bit read/write register
accessible in privileged mode only.

Figure 3.77 shows the arrangement of bits in the register.

Figure 3.77. TLB Debug Control Register format

Table 3.175 shows the bit functions of the TLB Debug Control Register.

Table 3.175. TLB Debug Control Register bit functions

Bit range	Name	Description
[31:8]	-	Reserved. UNP/SBZ.
[7]	IMM	Instruction Main TLB Match: 0 = Instruction main TLB match enabled. This is the reset value. 1 = Instruction main TLB match disabled.
[6]	DMM	Data Main TLB Match: 0 = Data main TLB match enabled. This is the reset value. 1 = Data main TLB match disabled.
[5]	IML	Instruction Main TLB Load: 0 = Instruction main TLB load enabled. This is the reset value. 1 = Instruction main TLB load disabled.
[4]	DML	Data Main TLB Load: 0 = Data main TLB load enabled. This is the reset value. 1 = Data main TLB load disabled.
[3]	IUM	Instruction Unit Match (Instruction MicroTLB match): 0 = Instruction MicroTLB match enabled. This is the reset value. 1 = Instruction MicroTLB match disabled.
[2]	DUM	Data Unit Match (Data MicroTLB match): 1 = Data MicroTLB match disabled. 0 = Data MicroTLB match enabled. This is the reset value.
[1]	IUL	Instruction Unit Load (Instruction MicroTLB load): 1 = Instruction MicroTLB load and flush disabled. 0 = Instruction MicroTLB load and flush enabled. This is the reset value.
[0]	DUL	Data Unit Load (Data MicroTLB load): 1 = Data MicroTLB load and flush disabled. 0 = Data MicroTLB load and flush enabled. This is the reset value.

Note

Because the ARM1136JF-S processor has a unified main TLB, you must always set the IMM bit to the same value as the DMM bit, and the IML bit to the same value as the DML bit. If you do not do this the result of TLB operations is Unpredictable.

Accessing the TLB Debug Control Register

Table 3.176 shows the results of attempted accesses to the TLB Debug Control Register for each mode.

Table 3.176. Results of accesses to the TLB Debug Control Register

Privileged read	Privileged write	User read or write
Data read	Data write	Undefined exception

To access the TLB Debug Control Register you read or write CP15 with:

Opcode_1 set to 7
CRn set to c15
CRm set to c1
Opcode_2 set to 0.

For example:

MRC p15, 7, <Rd>, c15, c1, 0          ; Read TLB Debug Control Register

MCR p15, 7, <Rd>, c15, c1, 0          ; Write to TLB Debug Control Register

See MicroTLB debug for a description of using the TLB Debug Control Register when debugging the MicroTLBs, and Main TLB debug for a description of using the TLB Debug Control Register when debugging the main TLBs.

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