ARM1136JF-S™ and ARM1136J-S™ Technical Reference Manual 1.8.2. Thumb instruction set summary

1.8.2. Thumb instruction set summary

The Thumb instruction set summary is given in Table 1.15.

Table 1.15. Thumb instruction set summary

Operation			Assembler
Move	Immediate, update flags		`MOV <Rd>, #<immed_8>`
	LowReg to LowReg, update flags		`MOV <Rd>, <Rm>`
	HighReg to LowReg		`MOV <Rd>, <Rm>`
	LowReg to HighReg		`MOV <Rd>, <Rm>`
	HighReg to HighReg		`MOV <Rd>, <Rm>`
Arithmetic	Add		`ADD <Rd>, <Rn>, #<immed_3>`
	Add immediate		`ADD <Rd>, #<immed_8>`
	Add LowReg and LowReg, update flags		`ADD <Rd>, <Rn>, <Rm>`
	Add HighReg to LowReg		`ADD <Rd>, <Rm>`
	Add LowReg to HighReg		`ADD <Rd>, <Rm>`
	Add HighReg to HighReg		`ADD <Rd>, <Rm>`
	Add immediate to PC		`ADD <Rd>, PC, #<immed_8*4>`
	Add immediate to SP		`ADD <Rd>, SP, #<immed_8*4>`
	Add immediate to SP		`ADD SP, #<immed_74>` `ADD SP, SP, #<immed_74>`
	Add with carry		`ADC <Rd>, <Rs>`
	Subtract immediate		`SUB <Rd>, <Rn>, #<immed_3>`
	Subtract immediate		`SUB <Rd>, #<immed_8>`
	Subtract		`SUB <Rd>, <Rn>, <Rm>`
	Subtract immediate		`SUB SP, #<immed_8>`
	Subtract immediate from SP		`SUB <Rd>, #<immed_7*4>`
	Subtract with carry		`SBC <Rd>, <Rm>`
	Negate		`NEG <Rd>, <Rm>`
	Multiply		`MUL <Rd>, <Rm>`
Compare	Compare immediate		`CMP <Rn>, #<immed_8>`
	Compare LowReg and LowReg, update flags		`CMP <Rn>, <Rm>`
	Compare LowReg and HighReg		`CMP <Rn>, <Rm>`
	Compare HighReg and LowReg		`CMP <Rn>, <Rm>`
	Compare HighReg and HighReg		`CMP <Rn>, <Rm>`
	Compare negative		`CMN <Rn>, <Rm>`
Logical	AND		`AND <Rd>, <Rm>`
	XOR		`EOR <Rd>, <Rm>`
	OR		`ORR <Rd>, <Rm>`
	Bit clear		`BIC <Rd>, <Rm>`
	Move NOT		`MVN <Rd>, <Rm>`
	Test bits		`TST <Rd>, <Rm>`
Shift/Rotate	Logical shift left		`LSL <Rd>, <Rm>, #<immed_5>` `LSL <Rd>, <Rs>`
	Logical shift right		`LSR <Rd>, <Rm>, #<immed_5>` `LSR <Rd>, <Rs>`
	Arithmetic shift right		`ASR <Rd>, <Rm>, #<immed_5>` `ASR <Rd>, <Rs>`
	Rotate right		`ROR <Rd>, <Rs>`
Branch	Conditional		`B{cond} <label>`
	Unconditional		`B <label>`
	Branch with link		`BL <label>`
	Branch, link and exchange		`BLX <label>`
	Branch, link and exchange		`BLX <Rm>`
	Branch and exchange		`BX <Rm>`
Load	With immediate offset		-
		Word	`LDR <Rd>, [<Rn>, #<immed_5>]`
		Halfword	`LDRH <Rd>, [<Rn>, #<immed_5*2>]`
		Byte	`LDRB <Rd>, [<Rn>, #<immed_5*4>]`
	With register offset		-
		Word	`LDR <Rd>, [<Rn>, <Rm>]`
		Halfword	`LDRH <Rd>, [<Rn>, <Rm>]`
		Signed halfword	`LDRSH <Rd>, [<Rn>, <Rm>]`
		Byte	`LDRB <Rd>, [<Rn>, <Rm>]`
		Signed byte	`LDRSB <Rd>, [<Rn>, <Rm>]`
		PC-relative	`LDR <Rd>, [PC, #<immed_8*4>]`
		SP-relative	`LDR <Rd>, [SP, #<immed_8*4>]`
		Multiple	`LDMIA <Rn>!, <reglist>`
Store	With immediate offset		-
		Word	`STR <Rd>, [<Rn>, #<immed_5*4>]`
		Halfword	`STRH <Rd>, [<Rn>, #<immed_5*2>]`
		Byte	`STRB <Rd>, [<Rn>, #<immed_5>]`
	With register offset		-
		Word	`STR <Rd>, [<Rn>, <Rm>]`
		Halfword	`STRH <Rd>, [<Rn>, <Rm>]`
		Byte	`STRB <Rd>, [<Rn>, <Rm>]`
		SP-relative	`STR <Rd>, [SP, #<immed_8*4>]`
		Multiple	`STMIA <Rn>!, <reglist>`
Push/Pop	Push registers onto stack		`PUSH <reglist>`
	Push LR and registers onto stack		`PUSH <reglist, LR>`
	Pop registers from stack		`POP <reglist>`
	Pop registers and PC from stack		`POP <reglist, PC>`
Change state	Change processor state		`CPS <effect> <iflags>`
Change state	Change endianness		`SETEND <endian_specifier>`
Byte-reverse	Byte-reverse word		`REV <Rd>, <Rm>`
	Byte-reverse halfword		`REV16 <Rd>, <Rm>`
	Byte-reverse signed halfword		`REVSH <Rd>, <Rm>`
Software interrupt			`SWI <immed_8>`
Software breakpoint			`BKPT <immed_8>`
Sign or zero extend	Sign extend 16 to 32		`SEXT16 <Rd>, <Rm>`
	Sign extend 8 to 32		`SEXT8 <Rd>, <Rm>`
	Zero extend 16 to 32		`UEXT16 <Rd>, <Rm>`
	Zero extend 8 to 32		`UEXT8 <Rd>, <Rm>`

Copyright © 2002-2006 ARM Limited. All rights reserved.	ARM DDI 0211I
Non-Confidential
PDF version