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The DCC is defined as the set of resources that the external DBGTAP debugger uses to communicate with a piece of software running on the core.
The DCC in the ARM1136JF-S processor is implemented using the two physically separate DTRs and a full/empty bit pair to augment each register, creating a bidirectional data port. One register can be read from the DBGTAP and is written from the processor. The other register is written from the DBGTAP and read by the processor. The full/empty bit pair for each register is automatically updated by the debug unit hardware, and is accessible to both the DBGTAP and to software running on the processor.
At the core side, the DCC resources are the following:
CP14 Debug Transfer Register c5 (DTR). Data coming from a DBGTAP debugger can be read by an MRC or STC instruction addressed to this register. The core can write to this register any data intended for the DBGTAP debugger, using an MCR or LDC instruction. Because the DTR comprises both a read (rDTR) and a write portion (wDTR), a piece of data written by the core and another coming from the DBGTAP debugger can be held in this register at the same time.
Some flags and control bits in CP14 Debug Status and Control Register c1 (DSCR):
User mode access to DCC disable bit. If this bit is set, only privileged software can access the DCC. That is, access the DSCR and the DTR.
The wDTRfull flag. When clear, this flag indicates to the core that the wDTR is ready to receive data from the core.
The rDTRfull flag. When set, this flag indicates to the core that there is data available to read at the DTR.
At the DBGTAP side, the resources are the following:
Scan chain 5 (see Scan chain 5). The only part of this scan chain that it is not used for the DCC is the Ready flag. The rest of the scan chain is to be used in the following way:
When the DBGTAPSM goes through the Update-DR state with EXTEST and scan chain 5 selected, and the nRetry flag set, the contents of the Data field are loaded into the rDTR. This is how the DBGTAP debugger sends data to the software running on the core.
When the DBGTAPSM goes through the Capture-DR state with INTEST and scan chain 5 selected, the contents of the wDTR are loaded into the Data field of the scan chain. This is how the DBGTAP debugger reads the data sent by the software running on the core.
When set, this flag indicates to the DBGTAP debugger that the contents of the wDTR that it has just captured are valid.
When set, this flag indicates to the DBGTAP debugger that the scanned-in Data field has been successfully written into the rDTR at the Update-DR state.