ARM1136JF-S™ and ARM1136J-S™ Technical Reference Manual 13.8.1. Behavior of the PC in debug state

13.8.1. Behavior of the PC in debug state

In debug state:

The PC is frozen on entry to debug state. That is, it does not increment on the execution of ARM instructions. However, branches and instructions that modify the PC directly do update it.
If the PC is read after the processor has entered debug state, it returns a value as described in Table 13.33, depending on the previous state and the type of debug event.
If a sequence for writing a certain value to the PC is executed while in debug state, and then the processor is forced to restart, execution starts at the address corresponding to the written value. However, the CPSR has to be set to the return ARM, Thumb, or Java state before the PC is written to, otherwise the processor behavior is Unpredictable.
If the processor is forced to restart without having performed a write to the PC, the restart address is Unpredictable.
If the PC or CPSR are written to while in debug state, subsequent reads to the PC return an Unpredictable value.
If a conditional branch is executed and it fails its condition code, an Unpredictable value is written to the PC.

Note

If you switch the ARM1136JF-S processor from ARM to Java state while in debug state, R[15:9] is cleared. If you want keep all processor state, you must save R5 before the switch and then restore the saved value of R5 when the processor is in Java state.

Table 13.33 shows the read PC value after debug state entry for different debug events.

Table 13.33. Read PC value after debug state entry

Debug event	ARM	Thumb	Java	Return address (RA^[1]) meaning
Breakpoint	RA+8	RA+4	RA	Breakpointed instruction address
Watchpoint	RA+8	RA+4	RA	Address of the instruction where the execution resumes (several instructions after the one that hit the watchpoint)^[2]
BKPT instruction	RA+8	RA+4	RA	BKPT instruction address
Vector catch	RA+8	RA+4	RA	Vector address
EDBGRQ signal activation	RA+8	RA+4	RA	Address of the instruction where the execution resumes
Debug state entry request command	RA+8	RA+4	RA	Address of the instruction where the execution resumes
^[1]This is the address of the first instruction the processor must executes on debug state exit. ^[2]With the ARM1136JF-S processor, watchpoints are imprecise. RA might not be the address of the instruction that follows the one that hit the watchpoint, because the processor might stop a number of instructions later. The address of the instruction that hit the watchpoint is in the CP15 WFAR.

Copyright © 2002-2006 ARM Limited. All rights reserved.	ARM DDI 0211I
Non-Confidential
PDF version