The level one DMA provides a background route to transfer blocks of data to or from the TCMs. It is used to move large blocks, rather than individual words or small structures.

The level one DMA is initiated and controlled by accessing the appropriate CP15 registers and instructions, see c11, DMA registers overview. The process specifies the internal start and end addresses and external start address, together with the direction of the DMA. The addresses specified are Virtual Addresses, and the level one DMA hardware includes translation of Virtual Addresses to Physical Addresses and checking of protection attributes.

The TLB, described in TLB organization is used to hold the page table entries for the DMA, and ensures that the entries in a TLB used by the DMA are consistent with the page tables. Errors arising from protection checks are signaled to the processor using an interrupt. Completion of the DMA can also be configured by software to signal the processor with an interrupt using the same interrupt to the processor that the error uses.

The status of the DMA is read from the CP15 registers associated with the DMA.

The DMA controller is programmed using the CP15 coprocessor. DMA accesses can only be to or from the TCM, configured as Local RAM, and must not be from areas of memory that can be contained in the caches. That is, no coherency support is provided in the caches.

The ARM1136JF-S processor implements two DMA channels. Only one channel can be active at a time. The key features of the DMA system are:

For some DMA events an interrupt is generated. If this happens the nDMAIRQ signal of the ARM1136JF-S processor is asserted. You can route this output pin to an external interrupt controller for prioritization and masking. This is the only mechanism by which the interrupt is signaled to the core.

Each DMA channel has its own set of control and status registers. The maximum number of DMA channels that can be defined is architecturally limited to 2. Only 1 DMA channel can be active at a time. If the other DMA channel has been started, it is queued to start performing memory operations after the currently active channel has completed.

The level one DMA behaves as a distinct master from the rest of the processor, and the same mechanisms for handling Shared memory regions must be used if the external addresses being accessed by the level one DMA system are also accessed by the rest of the processor. These are described in Memory attributes and types. If a User mode DMA transfer is performed using an external address that is not marked as Shared, an error is signaled by the DMA channel.

There is no ordering requirement of memory accesses caused by the level one DMA relative to those generated by reads and writes by the processor, while a channel is running. When a channel has completed running, all its transactions are visible to all other observers in the system. All memory accesses caused by the DMA occur in the order specified by the DMA channel, regardless of the memory type.

If a DMA is performed to Strongly Ordered memory (see Memory attributes and types), then a transaction caused by the DMA prevents any further transactions being generated by the DMA until the point at which the access is complete. A transaction is complete when it has changed the state of the target location or data has been returned to the DMA.

If the FCSE PID, the Domain Access Control Register, or the page table mappings are changed, or the TLB is flushed, while a DMA channel is in the Running or Queued state, then it is Unpredictable when the effect of these changes is seen by the DMA.