7.3. Tightly-coupled memory

The TCM is designed to provide low-latency memory that can be used by the processor without the unpredictability that is a feature of caches.

You can use such memory to hold critical routines, such as interrupt handling routines or real-time tasks where the indeterminacy of a cache is highly undesirable. In addition you can used it to hold scratch pad data, data types whose locality properties are not well suited to caching, and critical data structures such as interrupt stacks.

You can configure the TCM in several ways:

The TCM Status Register in CP15 c0 describes what TCM options and TCM sizes can be implemented, see c0, TCM Status Register.

Each TCM can optionally support a SmartCache mode of operation, see SmartCache behavior . In this mode the RAM behaves as a large contiguous area of cache, starting at the base address. As a result, the corresponding memory locations must also exist in the external memory system.

When a TCM is configured as a SmartCache it has the same:

If a TCM is not configured to operate as SmartCache, then it behaves as Local RAM, see Local RAM behavior. Each Data TCM is implemented in parallel with the Data Cache and the Instruction TCM is implemented in parallel with the Instruction Cache. Each TCM has a single movable base address, specified in CP15 register c9, (see c9, Data TCM Region Register and c9, Instruction TCM Region Register).

The size of each TCM can be different to the size of a cache way, but forms a single contiguous area of memory. The entire level one memory system is shown in Figure 7.1.

You can disable each TCM to avoid an access being made to it. This gives a reduction in the power consumption. You can disable each TCM independently from the enabling of the associated cache, as determined by CP15 register c9.

The disabling of a TCM invalidates the base address, so there is no unexpected hit behavior for the TCM when configured as Local RAM.

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