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| Home > Introduction > About the ARM1136JF-S processor |
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The ARM1136JF-S processor incorporates an integer unit that implements the ARM architecture v6. It supports the ARM and Thumb instruction sets, Jazelle technology to enable direct execution of Java bytecodes, and a range of SIMD DSP instructions that operate on 16-bit or 8-bit data values in 32-bit registers.
The ARM1136JF-S processor is a high-performance, low-power, ARM cached processor macrocell that provides full virtual memory capabilities.
The ARM1136JF-S processor features:
an integer unit with integral EmbeddedICE-RT logic
an eight-stage pipeline
branch prediction with return stack
low interrupt latency
external coprocessor interface and coprocessors 14 and 15
Instruction and Data Memory Management Units (MMUs), managed using MicroTLB structures backed by a unified Main TLB
Instruction and data caches, including a non-blocking data cache with Hit-Under-Miss (HUM)
the caches are virtually indexed and physically addressed
64-bit interface to both caches
a bypassable write buffer
level one Tightly-Coupled Memory (TCM) that can be used as a local RAM with DMA, or as SmartCache
high-speed Advanced Microprocessor Bus Architecture (AMBA) level two interfaces supporting prioritized multiprocessor implementations
Vector Floating-Point (VFP) coprocessor support
external coprocessor support
trace support
JTAG-based debug.
The only difference between the ARM1136JF-S and ARM1136J-S processor is that the ARM1136JF-S processor includes a Vector Floating-Point (VFP) coprocessor.
| Copyright © 2002-2006 ARM Limited. All rights reserved. | ARM DDI 0211I |
| Non-Confidential | |
| PDF version | |
| Home > Introduction > About the ARM1136JF-S processor |