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The purpose of the TLB Operations Register is to manage the Translation Lookaside Buffer (TLB). It is used to invalidate TLB entries, and you use it to do one of:
invalidate all the unlocked entries in the TLB
invalidate all TLB entries for an area of memory, before the MMU remaps it
invalidate all TLB entries that match an ASID value.
In general, when you access the TLB Operations Register, you choose whether to operate on:
Instruction TLB
Data TLB
Unified TLB.
The ARM1136JF-S processor has a unified TLB. Any TLB operations specified for the Instruction or Data TLB perform the equivalent operation on the unified TLB.
The TLB Operations Register is:
in CP15 c8
a 32-bit write-only register
accessible in privileged mode only.
Table 3.90 shows the results of attempted accesses to the TLB Operations Register for each mode.
Table 3.90. Results of accesses to the TLB Operations Register
| Privileged read | Privileged write | User read or write |
|---|---|---|
| Undefined exception | Data write | Undefined exception |
To access the TLB Operations Register you write CP15 with:
Opcode_1 set to 0
CRn set to c8
CRm set to:
c5, Instruction TLB
c6, Data TLB
c7, Unified TLB
Opcode_2 set to:
0, Invalidate TLB unlocked entries
1, Invalidate TLB Entry by MVA
2, Invalidate TLB Entry on ASID Match.
For example, to invalidate all the unlocked entries in the Instruction TLB:
MCR p15,0,<Rd>,c8, c5, 0 ; Write TLB Operations Register
Functions that update the contents of the TLB are executed in program order. Therefore, an explicit data access before the TLB Operations Register access uses the old TLB contents, and an explicit data access after the TLB Operations Register access uses the new TLB contents. For instruction accesses, TLB updates are guaranteed to have taken effect before the next pipeline flush. This includes flush prefetch buffer operations and exception return sequences.
Invalidate TLB unlocked entries invalidates all the unlocked entries in the TLB. This function causes a flush of the prefetch buffer. Therefore, all instructions that follow are fetched after the TLB invalidation.
When you invalidate TLB unlocked entries, c8 register bits[31:0] SBZ.
You can use Invalidate TLB Entry by MVA to invalidate all TLB entries for an area of memory before you remap.
You must perform an Invalidate TLB Entry by MVA of an MVA in each area you want to remap (section, small page, or large page).
This function invalidates a TLB entry that matches the provided MVA and ASID, or a global TLB entry that matches the provided MVA.
This function invalidates a matching locked entry.
The Invalidate TLB Entry by MVA operation uses an MVA and ASID as an argument. Figure 3.43 shows the c8 register format for this.
This is a single interruptible operation that invalidates all TLB entries that match the provided ASID value.
This function invalidates locked entries but does not invalidate entries marked as global.
In this processor this operation takes several cycles to complete and the instruction is interruptible. When interrupted the r14 state is set to indicate that the MCR instruction has not executed. Therefore, r14 points to the address of the MCR + 4. The interrupt routine then automatically restarts at the MCR instruction.
If the processor interrupts and later restarts this operation, any entries fetched into the TLB by the interrupt that uses the provided ASID are invalidated by the restarted invalidation.
The Invalidate TLB Entry on ASID Match function requires an ASID as an argument. Figure 3.44 shows the c8 register format for this.
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