ARM1136JF-S™ and ARM1136J-S™ Technical Reference Manual 3.2.1. Register allocation

3.2.1. Register allocation

Table 3.2 lists the registers and operations described in this section, arranged numerically, and gives the register reset values. In this table:

CRn is the register number within CP15
Op1 is the Opcode_1 value for the register
CRm is the operational register
Op2 is the Opcode_2 value for the register
The Type column holds one or more of these abbreviations:
NA
No access
RO
Read-only access from user and privileged modes
RO
Read-only access from privileged mode only
R/W
Read/write access from user and privileged modes
R/W
Read/write access from privileged mode only
WO
Write-only access from user and privileged modes
WO
Write-only access from privileged mode only
X
Access depends on another register or external signal.

Table 3.2. Summary of CP15 registers and operations

CRn	Op1	CRm	Op2	Register/operation name	Type	Reset value	Description
c0	0	c0	0	Main ID^[1]	RO	`0x4117B360`	c0, Main ID Register
			1	Cache Type	RO	Implementation-defined^[2]	c0, Cache Type Register
			2	TCM Status	RO	`0x00010001`	c0, TCM Status Register
			3	TLB Type	RO	`0x00080800`	c0, TLB Type Register
		c1	0	Processor Feature 0^[3]	RO	`0x00000111`	c0, Processor Feature Register 0
			1	Processor Feature 1^[3]	RO	`0x00000001`	c0, Processor Feature Register 1
			2	Debug Feature 0^[3]	RO	`0x00000002`	c0, Debug Feature Register 0
			3	Auxiliary Feature 0^[3]	RO	`0x00000000`	c0, Auxiliary Feature Register 0
			4	Memory Model Feature 0^[3]	RO	`0x01130003`	c0, Memory Model Feature Register 0
			5	Memory Model Feature 1^[3]	RO	`0x10030302`	c0, Memory Model Feature Register 1
			6	Memory Model Feature 2^[3]	RO	`0x01222110`	c0, Memory Model Feature Register 2
			7	Memory Model Feature 3^[3]	RO	`0x00000000`	c0, Memory Model Feature Register 3
		c2	0	Instruction Set Attributes 0^[3]	RO	`0x00140011`	c0, Instruction Set Attributes Register 0
			1	Instruction Set Attributes 1^[3]	RO	`0x12002111`	c0, Instruction Set Attributes Register 1
			2	Instruction Set Attributes 2^[3]	RO	`0x11231111`	c0, Instruction Set Attributes Register 2
			3	Instruction Set Attributes 3^[3]	RO	`0x01102131`	c0, Instruction Set Attributes Register 3
			4	Instruction Set Attributes 4^[3]	RO	`0x00000141`	c0, Instruction Set Attributes Register 4
			5	Instruction Set Attributes 5^[3]	RO	`0x00000000`	c0, Instruction Set Attributes Register 5
c1	0	c0	0	Control	R/W	`0x0xx5x0x8`^[4]	c1, Control Register
			1	Auxiliary Control	R/W	`0x00000007`	c1, Auxiliary Control Register
			2	Coprocessor Access Control	R/W	`0x00000000`	c1, Coprocessor Access Control Register
c2	0	c0	0	Translation Table Base 0	R/W	`0x00000000`	c2, Translation Table Base Register 0, TTBR0
			1	Translation Table Base 1	R/W	`0x00000000`	c2, Translation Table Base Register 1, TTBR1
			2	Translation Table Base Control	R/W	`0x00000000`	c2, Translation Table Base Control Register, TTBCR
c3	0	c0	0	Domain Access Control	R/W	`0x00000000`	c3, Domain Access Control Register
c4	-	-	-	Not used	-	-	-
c5	0	c0	0	Data Fault Status	R/W	`0x00000000`	c5, Data Fault Status Register, DFSR
c5	0	c0	1	Instruction Fault Status	R/W	`0x00000000`	c5, Instruction Fault Status Register, IFSR
c6	0	c0	0	Data Fault Address	R/W	`0x00000000`	c6, Fault Address Register, FAR
c6	0	c0	1	Watchpoint Fault Address	R/W	`0x00000000`	c6, Watchpoint Fault Address Register, WFAR
c7	0	c0	4	Wait For Interrupt	WO	-	c7, Cache Operations Register
		c5	0	Invalidate Entire Instruction Cache	WO	-	c7, Cache Operations Register
			1	Invalidate Instruction Cache, using MVA	WO	-	c7, Cache Operations Register
			2	Invalidate Instruction Cache, using Set/Way	WO	-	c7, Cache Operations Register
			4	Flush Prefetch Buffer	WO^[5]	-	c7, Cache Operations Register
			6	Flush Entire Branch Target Cache	WO	-	c7, Cache Operations Register
			7	Flush Branch Target Cache Entry	WO	-	c7, Cache Operations Register
		c6	0	Invalidate Entire Data Cache	WO	-	c7, Cache Operations Register
			1	Invalidate Data Cache Line, using MVA	WO	-	c7, Cache Operations Register
			2	Invalidate Data Cache Line, using Set/Way	WO	-	c7, Cache Operations Register
		c7	0	Invalidate Both Caches	WO	-	c7, Cache Operations Register
c7	0	c10	0	Clean Entire Data Cache	WO	-	c7, Cache Operations Register
			1	Clean Data Cache Line, using MVA	WO	-	c7, Cache Operations Register
			2	Clean Data Cache Line, using Set/Way	WO	-	c7, Cache Operations Register
			4	Data Synchronization Barrier	WO^[5]	-	c7, Cache Operations Register
			5	Data Memory Barrier	WO^[5]	-	c7, Cache Operations Register
			6	Read Cache Dirty Status Register	RO	`0x00000000`	c7, Cache Operations Register
		c12	4	Read Block Transfer Status Register	RO^[5]	`0x00000000`	c7, Cache Operations Register
		c12	5	Stop Prefetch Range	WO^[5]	-	c7, Cache Operations Register
		c13	1	Prefetch Instruction Cache Line	WO	-	c7, Cache Operations Register
		c14	0	Clean and Invalidate Entire Data Cache	WO	-	c7, Cache Operations Register
			1	Clean and Invalidate Data Cache Line, using MVA	WO	-	c7, Cache Operations Register
			2	Clean and Invalidate Data Cache Line, using Set/Way	WO	-	c7, Cache Operations Register
c8	0	c5	0	Invalidate Instruction TLB	WO	-	c8, TLB Operations Register (invalidate TLB operation)
			1	Invalidate Instruction TLB Single Entry	WO	-	c8, TLB Operations Register (invalidate TLB operation)
			2	Invalidate Instruction TLB Entry on ASID match	WO	-	c8, TLB Operations Register (invalidate TLB operation)
		c6	0	Invalidate Data TLB	WO	-	c8, TLB Operations Register (invalidate TLB operation)
			1	Invalidate Data TLB Single Entry	WO	-	c8, TLB Operations Register (invalidate TLB operation)
			2	Invalidate Data TLB Entry on ASID match	WO	-	c8, TLB Operations Register (invalidate TLB operation)
		c7	0	Invalidate Unified TLB	WO	-	c8, TLB Operations Register (invalidate TLB operation)
			1	Invalidate Unified TLB Single Entry	WO	-	c8, TLB Operations Register (invalidate TLB operation)
			2	Invalidate Unified TLB Entry on ASID match	WO	-	c8, TLB Operations Register (invalidate TLB operation)
c9	0	c0	0	Data Cache Lockdown	R/W	`0xFFFFFFF0`	c9, Data and Instruction Cache Lockdown Registers
		c0	1	Instruction Cache Lockdown	R/W	`0xFFFFFFF0`	c15, Cache and Main TLB Master Valid Registers
		c1	0	Data TCM Region	R/W	Implementation-defined^[6]	c9, Data TCM Region Register
		c1	1	Instruction TCM Region	R/W	Implementation-defined^[6]	c9, Instruction TCM Region Register
c10	0	c0	0	TLB Lockdown	R/W	`0x00000000`	c10, TLB Lockdown Register
		c2	0	Primary Region Remap (PMRR)^[3]	R/W	`0x0009AAA4`	Primary Region Remap Register (PRRR)
		c2	1	Normal Memory Remap (NMRR)^[3]	R/W	`0x44E048E0`	Normal Memory Remap Register (NMRR)
c11	0	c0	0	DMA Identification and Status (Present)	RO	`0x00000003`	c11, DMA Identification and Status Registers
			1	DMA Identification and Status (Queued)	RO	`0x00000000`	c11, DMA Identification and Status Registers
			2	DMA Identification and Status (Running)	RO	`0x00000000`	c11, DMA Identification and Status Registers
			3	DMA Identification and Status (Interrupting)	RO	`0x00000000`	c11, DMA Identification and Status Registers
		c1	0	DMA User Accessibility	R/W	`0x00000000`	c11, DMA User Accessibility Register
		c2	0	DMA Channel Number	R/W^[5]	`0x00000000`	c11, DMA Channel Number Register
		c3	0	DMA Enable (Stop)	WO^[5], X^[7]	-	c11, DMA Enable Registers
			1	DMA Enable (Start)	WO^[5], X^[7]	-	c11, DMA Enable Registers
			2	DMA Enable (Clear)	WO^[5], X^[7]	-	c11, DMA Enable Registers
		c4	0	DMA Control	R/W^[5], X^[7]	`0x00000000`	c11, DMA Control Registers
		c5	0	DMA Internal Start Address	R/W^[5], X^[7]	`0x00000000`	c11, DMA Internal Start Address Registers
		c6	0	DMA External Start Address	R/W^[5], X^[7]	`0x00000000`	c11, DMA External Start Address Registers
		c7	0	DMA Internal End Address	R/W^[5], X^[7]	`0x00000000`	c11, DMA Internal End Address Registers
		c8	0	DMA Channel Status	RO^[5], X^[7]	`0x00000000`	c11, DMA Channel Status Registers
		c15	0	DMA Context ID	R/W	`0x00000000`	c11, DMA Context ID Registers
c12	-	-	-	Not used	-	-	-
c13	0	c0	0	FCSE PID	R/W	`0x00000000`	c13, FCSE PID Register
			1	Context ID	R/W	`0x00000000`	c13, Context ID Register
			2	User Read/Write Thread and Process ID^[3]	R/W^[5]	`0x00000000`	c13, Thread and process ID registers
			3	User Read-only Thread and Process ID^[3]	R/W^[5]	`0x00000000`	c13, Thread and process ID registers
			4	Privileged Only Thread and Process ID^[3]	R/W	`0x00000000`	c13, Thread and process ID registers
c14	-	-	-	Not used	-	-	-
c15	0	c2	0	Data Memory Remap	R/W	`0x01C97CC8`	c15, Memory remap registers
			1	Instruction Memory Remap	R/W	`0x01C97CC8`	c15, Memory remap registers
			2	DMA Memory Remap	R/W	`0x01C97CC8`	c15, Memory remap registers
			4	Peripheral Port Memory Remap	R/W	`0x01C97CC8`	c15, Memory remap registers
		c12	0	Performance Monitor Control	R/W	`0x00000000`	c15, Performance Monitor Control Register (PMNC)
			1	Cycle Counter (CCNT)	R/W	Unpredictable	c15, Cycle Counter Register (CCNT)
			2	Count 0 (PMN0)	R/W	`0x00000000`	c15, Count Register 0 (PMN0)
			3	Count 1 (PMN1)	R/W	`0x00000000`	c15, Count Register 1 (PMN1)
	3	c0	0	Data Debug Cache	RO	`0x00000000`	c15, Cache debug operations registers
			1	Instruction Debug Cache	RO	`0x00000000`	c15, Cache debug operations registers
		c2	0	Data Tag RAM Read Operation	WO	-	c15, Cache debug operations registers
			1	Instruction Tag RAM Read Operation	WO	-	c15, Cache debug operations registers
		c4	1	Instruction Cache Data RAM Read Operation	WO	-	c15, Cache debug operations registers
		c8	<R>^[8]	Instruction Cache Master Valid	R/W	`0x00000000`	c15, Cache and Main TLB Master Valid Registers
		c10	<R>^[8]	Instruction SmartCache Master Valid	R/W	`0x00000000`	c15, Cache and Main TLB Master Valid Registers
		c12	<R>^[8]	Data Cache Master Valid	R/W	`0x00000000`	c15, Cache and Main TLB Master Valid Registers
		c14	<R>^[8]	Data SmartCache Master Valid	R/W	`0x00000000`	c15, Cache and Main TLB Master Valid Registers
c15	5	c4	0	Data MicroTLB Index	R/W	`0x00000000`	c15, Instruction MicroTLB and Data MicroTLB Index Registers
			1	Instruction MicroTLB Index	R/W	`0x00000000`	c15, Instruction MicroTLB and Data MicroTLB Index Registers
			2	Read Main TLB Entry	WO	`0x00000000`	c15, Main TLB Entry Registers (Main TLB index)
			4	Write Main TLB Entry	WO	`0x00000000`	c15, Main TLB Entry Registers (Main TLB index)
		c5	0	Data MicroTLB VA	RO	`0x00000000`	c15, TLB VA Registers
			1	Instruction MicroTLB VA	RO	`0x00000000`	c15, TLB VA Registers
			2	Main TLB VA	R/W	`0x00000000`	c15, TLB VA Registers
		c6	0	Data MicroTLB PA	RO	`0x00000000`	c15, TLB PA Registers
			1	Instruction MicroTLB PA	RO	`0x00000000`	c15, TLB PA Registers
			2	Main TLB PA	R/W	`0x00000000`	c15, TLB PA Registers
		c7	0	Data MicroTLB Attribute	RO	`0x00000000`	c15, TLB Attribute Registers
			1	Instruction MicroTLB Attribute	RO	`0x00000000`	c15, TLB Attribute Registers
			2	Main TLB Attribute	R/W	`0x00000000`	c15, TLB Attribute Registers
		c14	<R>^[8]	Main TLB Master Valid	R/W	`0x00000000`	c15, Cache and Main TLB Master Valid Registers
	7	c0	0	Cache Debug Control	R/W	`0x00000000`	c15, Cache Debug Control Register
	7	c1	0	TLB Debug Control	R/W	`0x00000000`	c15, TLB Debug Control Register
^[1]Before the r1p0 release, the Main ID register was called the ID Code Register. ^[2]The cache type reset value is determined by the size of the caches implemented. ^[3]These registers are only implemented from the rev1 (r1p0) release of the ARM1136JF-S processor. ^[4]On reset, the values of bits 25, 22, and 7 depend on the value of macrocell input signals BIGENDINIT and UBITINIT, and the value of bit 13 depends on the value of the VINITHI signal. See Control Register reset value. ^[5]Bold text denotes that the register can be accessed in User mode. ^[6]See register description for details. ^[7]User accessibility depends on the state of the DMA User Accessibility Register. ^[8]<R> = register number.

Operations available using MCRR instructions

A limited number of operations are available using MCRR instructions. These are accessed as shown:

MCRR{cond} p15,<Opcode_1>,<End Address>,<Start Address>,<CRm>

The operations available in this way are shown in Table 3.3:

Table 3.3. Summary of CP15 MCRR operations

Op1	CRm	Register or operation	Type^[1]	Reset value	Description
0	c5	Invalidate Instruction Cache Range	WO	-	Invalidate, Clean and Prefetch cache operations for address ranges
	c6	Invalidate Data Cache Range	WO	-	Invalidate, Clean and Prefetch cache operations for address ranges
	c12	Clean Data Cache Range	WO^[1]	-	Invalidate, Clean and Prefetch cache operations for address ranges
	c14	Clean and Invalidate Data Cache Range	WO	-	Invalidate, Clean and Prefetch cache operations for address ranges
1	c12	Prefetch Instruction Cache Range	WO^[1]	-	Invalidate, Clean and Prefetch cache operations for address ranges
2	c12	Prefetch Data Cache Range	WO^[1]	-	Invalidate, Clean and Prefetch cache operations for address ranges
^[1]Bold text denotes that the register can be accessed in User mode.

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