Bypasses the device by providing a path between DBGTDI and DBGTDO.

1 bit.

When the bypass instruction is the current instruction in the Instruction Register, serial data is transferred from DBGTDI to DBGTDO in the Shift-DR state with a delay of one TCK cycle. There is no parallel output from the Bypass Register. A logic 0 is loaded from the parallel input of the Bypass Register in the Capture-DR state. Nothing happens at the Update-DR state.

Figure 14.3 shows the operation of the Bypass Register.