ARM1136JF-S™ and ARM1136J-S™ Technical Reference Manual A.1. Global signals

A.1. Global signals

Table A.1 lists the ARM1136JF-S global signals.

Free clocks are the free running clocks with minimal insertion delay for clocking the clock gating circuitry. Free clocks must be balanced with the incoming clock signal, but not with the clocks clocking the core logic.

Table A.1. Global signals

Name	Direction	Description
CLKIN	Input	Core clock
FREECLKIN	Input	Free version of the core clock
FREEHCLKIRW	Input	Free version of HCLKIRW
FREEHCLKPD	Input	Free version of HCLKPD
HCLKDEN	Input	Clock enable for the DMA port to enable it to be clocked at a reduced rate
HCLKIRW	Input	HCLK for the I/R/W ports
HCLKIRWEN	Input	HCLKEN for the I/R/W ports
HCLKPD	Input	HCLK for the P/D ports
HCLKPEN	Input	Clock enable for the peripheral port to enable it to be clocked at a reduced rate
HRESETIRWn	Input	HRESETn for the I/R/W ports
HRESETPDn	Input	HRESETn for the P/D ports
HSYNCENIRW	Input	Synchronous control HCLK domain for I/R/W ports
HSYNCENPD	Input	Synchronous control HCLK domain for P/D ports
nPORESETIN	Input	Power on reset (resets debug logic)
nRESETIN	Input	Core reset
STANDBYWFI	Output	Indicates that the ARM1136JF-S processor is in Standby mode
SYNCENIRW	Input	Synchronous control CLKIN domain for IRW ports
SYNCENPD	Input	Synchronous control CLKIN domain for PD ports

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