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This section provides:
A key to the ARM and Thumb instruction set tables is given in Table 1.5.
The ARM1136JF-S processor is an implementation of the ARM architecture v6 with ARM Jazelle technology. For a description of the ARM and Thumb instruction sets, see the ARM Architecture Reference Manual. Contact ARM Limited for complete descriptions of all instruction sets.
Table 1.5. Key to instruction set tables
| Symbol | Description |
|---|---|
{!} | Update base register after operation if ! present. |
{^} | For all STMs and LDMs that do not load the PC, stores or restores the User mode banked registers instead of the current mode registers if ^ present, and sets the S bit. For LDMs that load the PC, indicates that the CPSR is loaded from the SPSR. |
B | Byte operation. |
H | Halfword operation. |
T | Forces execution to be handled as having User mode privilege. Cannot be used with pre-indexed addresses. |
x | Selects HIGH or LOW 16 bits of register Rm. T selects the HIGH 16 bits. (T = top) and B selects the LOW 16 bits (B = bottom). |
y | Selects HIGH or LOW 16 bits of register Rs. T selects the HIGH 16 bits. (T = top) and B selects the LOW 16 bits (B = bottom). |
{cond} | Updates condition flags if cond present. See Table 1.14. |
{field} | See Table 1.13. |
{S} | Sets condition codes (optional). |
<a_mode2> | See Table 1.7. |
<a_mode2P> | See Table 1.8. |
<a_mode3> | See Table 1.9. |
<a_mode4> | See Table 1.10. |
<a_mode5> | See Table 1.11. |
<cp_num> | One of the coprocessors p0 to p15. |
<effect> | Specifies what effect is wanted on the interrupt disable bits, A, I, and F in the CPSR: IE = Interrupt enable ID = Interrupt disable. If |
<endian_specifier> | BE = Set E bit in instruction, set CPSR E bit. LE = Reset E bit in instruction, clear CPSR E bit. |
<HighReg> | One of the registers r8 to r15. |
<iflags> | A sequence of one or more of the following: a = Set A bit i = Set I bit f = Set F bit. If |
<immed_8*4> | A 10-bit constant, formed by left-shifting an 8-bit value by two bits. |
<immed_8> | An 8-bit constant. |
<immed_8r> | A 32-bit constant, formed by right-rotating an 8-bit value by an even number of bits. |
<label> | The target address to branch to. |
<LowReg> | One of the registers R0 to r7. |
<mode> | The new mode number for a mode change. See Mode bits. |
<op1>, <op2> | Specify, in a coprocessor-specific manner, which coprocessor operation to perform. |
<operand2> | See Table 1.12. |
<option> | Specifies additional instruction options to the coprocessor. An integer in the range 0 to 255 surrounded by { and }. |
<reglist> | A comma-separated list of registers, enclosed in braces {and}. |
<rotation> | One of ROR #8, ROR
#16, or ROR #24. |
<shift> | 0 = LSL #N for N= 0 to 31 1 = ASR #N for N = 1 to 32. |
| Copyright © 2002-2006 ARM Limited. All rights reserved. | ARM DDI 0211I |
| Non-Confidential | |
| PDF version | |
| Home > Introduction > ARM1136JF-S instruction set summary |