The ARM1136JF-S level one memory system consists of:

In parallel with each of the caches is an area of dedicated RAM on both the instruction and data sides. These regions are called TCM. You can implement 0 or 1 TCM on each of the Instruction and Data sides.

Each TCM has a dedicated base address that you can place anywhere in the physical address map, and does not have to be backed by memory implemented externally. The Instruction and Data TCMs have separate base addresses.

Each TCM can optionally support a SmartCache mode of operation. In this mode of operation, the TCM behaves as a large contiguous area of cache, starting at the base address.

Each TCM not configured to operate as SmartCache can be accessed by a DMA mechanism to enable this memory to be loaded from or stored to another location in memory while the processor core is running.

The MMU provides the facilities required by sophisticated operating systems to deliver protected virtual memory environments and demand paging. It also supports real-time tasks with features that provide predictable execution time.

Address translation is handled in a full MMU for each of the instruction and data sides. The MMU is responsible for protection checking, address translation, and memory attributes, some of which can be passed to the level two memory system.

The memory translations are cached in MicroTLBs for each of the instruction and data sides and for the DMA, with a single Main TLB backing the MicroTLBs.