ARM1136JF-S™ and ARM1136J-S™ Technical Reference Manual 2.10.2. Load or Store Halfword Exclusive

2.10.2. Load or Store Halfword Exclusive

These instructions operate on naturally aligned, unsigned data of size halfword:

The address in memory must be 16-bit aligned, address[0] == b0
- The instruction generates an alignment fault if this condition is not met.
  For more information, see Operation of unaligned accesses.
The transaction must be a single access, or an indivisible burst if the bus width is less than 16 bits.

The LDREXH and STREXH instructions share the same data monitors as the LDREX and STREX instructions, a local and a global monitor for each processor, for shared memory support.

LDREXH

Figure 2.10 shows the format of the Load Register Halfword Exclusive, LDREXH, instruction.

Figure 2.10. LDREXH instruction

Syntax

LDREXH{<cond>} <Rd>, [<Rn>]

Operation

if ConditionPassed(cond) then

    processor_id = ExecutingProcessor()

    Rd = Memory[Rn,2]

    physical_address=TLB(Rn)

    if Shared(Rn) ==1 then

        MarkExclusiveGlobal(physical_address,processor_id,2)

    MarkExclusiveLocal(physical_address,processor_id,2)

Notes

The result of the LDREXH operation is UNPREDICTABLE if you specify register 15 for <Rd> or <Rn>
If a data abort occurs during an LDREXH operation it is UNPREDICTABLE whether the MarkExclusiveGlobal() or the MarkExclusiveLocal() operation is executed. However, Rd is not updated.
In regions of shared memory which do not support exclusives, the behavior of LDREXH is UNPREDICTABLE. This applies to regions of memory which do not have an exclusives monitor implemented.
This command is only available from the rev1 (r1p0) release of the ARM1136JF-S processor.

STREXH

Figure 2.11 shows the format of the Store Register Halfword Exclusive, STREXH, instruction.

Figure 2.11. STREXH instruction

Syntax

STREXH{<cond>} <Rd>, <Rm>, [<Rn>]

Operation

if ConditionPassed(cond) then

    processor_id = ExecutingProcessor()

    physical_address=TLB(Rn)

    if IsExclusiveLocal(physical_address,processor_id,2) then

        if Shared(Rn)==1 then

            if IsExclusiveGlobal(physical_address,processor_id,2) then

                Memory[Rn,2] = Rm

                Rd = 0

                ClearByAddress(physical_address,2)

            else

                Rd =1

        else

            Memory[Rn,2] = Rm

            Rd = 0

    else

        Rd = 1

    ClearExclusiveLocal(processor_id)

Notes

There is a register restriction that Rd != Rm and Rd != Rn.
The result of the STREXH operation is UNPREDICTABLE if you specify register 15 for <Rd>, <Rn> or <Rm>.
If a data abort occurs during a STREXH operation:
- Memory is not updated
- <Rd> is not updated
- it is UNPREDICTABLE whether the ClearExclusiveLocal() or the ClearByAddress() operation is executed.
In regions of shared memory which do not support exclusives, the behavior of STREXH is UNPREDICTABLE. This applies to regions of memory which do not have an exclusives monitor implemented.
This command is only available from the rev1 (r1p0) release of the ARM1136JF-S processor.

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