ARM1136JF-S™ and ARM1136J-S™ Technical Reference Manual 8.6.1. Stores on the AHB-Lite interface

8.6.1. Stores on the AHB-Lite interface

Table 8.80 to Table 8.104 show the values of HTRANSW, HADDRW, HBURSTW, HSIZEW, and HBSTRBW for Cachable or Noncachable Write-Through stores over the Data Write Interface.

Table 8.80. STRB

Address[4:0]	Endianess	HTRANSW	HADDRW	HBURSTW	HSIZEW	HBSTRBW
`0x00` (byte 0)	LE-8 or BE-8	Nseq	`0x00`	Single	8-bit	b00000001
`0x00` (byte 0)	BE-32	Nseq	`0x00`	Single	8-bit	b00001000
`0x01` (byte 1)	LE-8 or BE-8	Nseq	`0x01`	Single	8-bit	b00000010
`0x01` (byte 1)	BE-32	Nseq	`0x01`	Single	8-bit	b00000100
`0x02` (byte 2)	LE-8 or BE-8	Nseq	`0x02`	Single	8-bit	b00000100
`0x02` (byte 2)	BE-32	Nseq	`0x02`	Single	8-bit	b00000010
`0x03` (byte 3)	LE-8 or BE-8	Nseq	`0x03`	Single	8-bit	b00001000
`0x03` (byte 3)	BE-32	Nseq	`0x03`	Single	8-bit	b00000001
`0x04` (byte 4)	LE-8 or BE-8	Nseq	`0x04`	Single	8-bit	b00010000
`0x04` (byte 4)	BE-32	Nseq	`0x04`	Single	8-bit	b10000000
`0x05` (byte 5)	LE-8 or BE-8	Nseq	`0x05`	Single	8-bit	b00100000
`0x05` (byte 5)	BE-32	Nseq	`0x05`	Single	8-bit	b01000000
`0x06` (byte 6)	LE-8 or BE-8	Nseq	`0x06`	Single	8-bit	b01000000
`0x06` (byte 6	BE-32	Nseq	`0x06`	Single	8-bit	b00100000
`0x07` (byte 7)	LE-8 or BE-8	Nseq	`0x07`	Single	8-bit	b10000000
`0x07` (byte 7)	BE-32	Nseq	`0x07`	Single	8-bit	b00010000

Table 8.81. STRH

Address[4:0]	Endianess	HTRANSW	HADDRW	HBURSTW	HSIZEW	HBSTRBW
`0x00` (byte 0)	LE-8 or BE-8	Nseq	`0x00`	Single	16-bit	b00000011
`0x00` (byte 0)		Nseq	`0x00`	Single	16-bit	b00001100
`0x01` (byte 1)	LE-8 or BE-8	Nseq	`0x00`	Single	32-bit	b00000110^[1]
`0x01` (byte 1)		Nseq	`0x00`	Single	16-bit	b00001100^[2]
`0x02` (byte 2)	LE-8 or BE-8	Nseq	`0x02`	Single	16-bit	b00001100
`0x02` (byte 2)		Nseq	`0x02`	Single	16-bit	b00000011
`0x03` (byte 3)	LE-8 or BE-8	Nseq	`0x03`	Single	8-bit	b00001000
`0x03` (byte 3)	LE-8 or BE-8	Nseq	`0x04`	Single	8-bit	b00010000
`0x03` (byte 3)		Nseq	`0x02`	Single	16-bit	b00000011^[2]
`0x04` (byte 4)	LE-8 or BE-8	Nseq	`0x04`	Single	16-bit	b00110000
`0x04` (byte 4)		Nseq	`0x04`	Single	16-bit	b11000000
`0x05` (byte 5)	LE-8 or BE-8	Nseq	`0x04`	Single	32-bit	b01100000^[1]
`0x05` (byte 5)		Nseq	`0x04`	Single	16-bit	b11000000
`0x06` (byte 6)	LE-8 or BE-8	Nseq	`0x06`	Single	16-bit	b11000000
`0x06` (byte 6)		Nseq	`0x06`	Single	16-bit	b00110000^[2]
`0x07` (byte 7)	LE-8 or BE-8	Nseq	`0x07`	Single	8-bit	b10000000
`0x07` (byte 7)	LE-8 or BE-8	Nseq	`0x08`	Single	8-bit	b00000001
`0x07` (byte 7)		Nseq	`0x06`	Single	16-bit	b00110000^[2]
^[1]Denotes that HUNALIGNW is asserted for that transfer. This is only used for ARMv6 unaligned stores. ^[2]Denotes that this behavior is Unpredictable.

Table 8.82. STR or STM1

Address[4:0]	HTRANSW	HADDRW	HBURSTW	HSIZEW	HBSTRBW
`0x00` (byte 0) (word 0)	Nseq	`0x00`	Single	32-bit	b00001111
`0x01` (byte 1)	Nseq	`0x00`	Single	32-bit	b00001110^[1]
`0x01` (byte 1)	Nseq	`0x04`	Single	8-bit	b00010000
`0x02` (byte 2)	Nseq	`0x02`	Single	16-bit	b00001100
`0x02` (byte 2)	Nseq	`0x04`	Single	16-bit	b00110000
`0x03` (byte 3)	Nseq	`0x03`	Single	8-bit	b00001000
`0x03` (byte 3)	Nseq	`0x04`	Single	32-bit	b01110000^[1]
`0x04` (byte 4) (word 1)	Nseq	`0x04`	Single	32-bit	b11110000
`0x05` (byte 5)	Nseq	`0x04`	Single	32-bit	b11100000^[1]
`0x05` (byte 5)	Nseq	`0x08`	Single	8-bit	b00000001
`0x06` (byte 6)	Nseq	`0x06`	Single	16-bit	b11000000
`0x06` (byte 6)	Nseq	`0x08`	Single	16-bit	b00000011
`0x07` (byte 7)	Nseq	`0x07`	Single	8-bit	b10000000
`0x07` (byte 7)	Nseq	`0x08`	Single	32-bit	b00000111^[1]
`0x08` (byte 8) (word 2)	Nseq	`0x08`	Single	32-bit	b00001111
`0x0C` (word 3)	Nseq	`0x0C`	Single	32-bit	b11110000
`0x10` (word 4)	Nseq	`0x10`	Single	32-bit	b00001111
`0x14` (word 5)	Nseq	`0x14`	Single	32-bit	b11110000
`0x18` (word 6)	Nseq	`0x18`	Single	32-bit	b00001111
`0x1C` (word 7)	Nseq	`0x1C`	Single	32-bit	b11110000
^[1]Denotes that HUNALIGNW is asserted for that transfer. This is only used for ARMv6 unaligned stores.

Table 8.83. STM2 to words 0, 1, 2, 3, 4, 5, or 6

Address[4:0]	HTRANSW	HADDRW	HBURSTW	HSIZEW	HBSTRBW
`0x00` (word 0)	Nseq	`0x00`	Single	64-bit	b11111111
`0x04` (word 1)	Nseq	`0x04`	Incr	32-bit	b11110000
`0x04` (word 1)	Seq	`0x08`	Incr	32-bit	b00001111
`0x08` (word 2)	Nseq	`0x08`	Single	64-bit	b11111111
`0x0C` (word 3)	Nseq	`0x0C`	Incr	32-bit	b11110000
`0x0C` (word 3)	Seq	`0x10`	Incr	32-bit	b00001111
`0x10` (word 4)	Nseq	`0x10`	Single	64-bit	b11111111
`0x14` (word 5)	Nseq	`0x14`	Incr	32-bit	b11110000
`0x14` (word 5)	Seq	`0x18`	Incr	32-bit	b00001111
`0x18` (word 6)	Nseq	`0x18`	Single	64-bit	b11111111

Table 8.84. STM2 to word 7

Address[4:0]	Operations
`0x1C`	`STR` to `0x1C` + `STR` to `0x00`

Table 8.85. STM3 to words 0, 1, 2, 3, 4, or 5

Address[4:0]	HTRANSW	HADDRW	HBURSTW	HSIZEW	HBSTRBW
`0x00` (word 0)	Nseq	`0x00`	Incr	32-bit	b00001111
	Seq	`0x04`			b11110000
	Seq	`0x08`			b00001111
`0x04` (word 1)	Nseq	`0x04`	Incr	32-bit	b11110000
	Seq	`0x08`			b00001111
	Seq	`0x0C`			b11110000
`0x08` (word 2)	Nseq	`0x08`	Incr	32-bit	b00001111
	Seq	`0x0C`			b11110000
	Seq	`0x10`			b00001111
`0x0C` (word 3)	Nseq	`0x0C`	Incr	32-bit	b11110000
	Seq	`0x10`			b00001111
	Seq	`0x14`			b11110000
`0x10` (word 4)	Nseq	`0x10`	Incr	32-bit	b00001111
	Seq	`0x14`			b11110000
	Seq	`0x18`			b00001111
`0x14` (word 5)	Nseq	`0x14`	Incr	32-bit	b11110000
	Seq	`0x18`			b00001111
	Seq	`0x1C`			b11110000

Table 8.86. STM3 to words 6 or 7

Address[4:0]	Operations
`0x18` (word 6)	`STM2` to `0x18` + `STR` to `0x00`
`0x1C` (word 7)	`STR` to `0x1C` + `STM2` to `0x00`

Table 8.87. STM4 to word 0, 1, 2, 3, or 4

Address[4:0]	HTRANSW	HADDRW	HBURSTW	HSIZEW	HBSTRBW
`0x00` (word 0)	Nseq	`0x00`	Incr	64-bit	b11111111
`0x00` (word 0)	Seq	`0x08`	Incr	64-bit	b11111111
`0x04` (word 1)	Nseq	`0x04`	Incr4	32-bit	b11110000
	Seq	`0x08`			b00001111
		`0x0C`			b11110000
		`0x10`			b00001111
`0x08` (word 2)	Nseq	`0x08`	Incr	64-bit	b11111111
`0x08` (word 2)	Seq	`0x10`	Incr	64-bit	b11111111
`0x0C` (word 3)	Nseq	`0x0C`	Incr4	32-bit	b11110000
	Seq	`0x10`			b00001111
		`0x14`			b11110000
		`0x18`			b00001111
`0x10` (word 4)	Nseq	`0x10`	Incr	64-bit	b11111111
`0x10` (word 4)	Seq	`0x18`	Incr	64-bit	b11111111

Table 8.88. STM4 to word 5, 6, or 7

Address[4:0]	Operations
`0x14` (word 5)	`STM3` to `0x14` + `STR` to `0x00`
`0x18` (word 6)	`STM2` to `0x18` + `STM2` to `0x00`
`0x1C` (word 7)	`STR` to `0x1C` + `STM3` to `0x00`

Table 8.89. STM5 to word 0, 1, 2, or 3

Address[4:0]	HTRANSW	HADDRW	HBURSTW	HSIZEW	HBSTRBW
`0x00` (word 0)	Nseq	`0x00`	Incr	32-bit	b00001111
	Seq	`0x04`			b11110000
		`0x08`			b00001111
		`0x0C`			b11110000
		`0x10`			b00001111
`0x04` (word 1)	Nseq	`0x04`	Incr	32-bit	b11110000
	Seq	`0x08`			b00001111
		`0x0C`			b11110000
		`0x10`			b00001111
		`0x14`			b11110000
`0x08` (word 2)	Nseq	`0x08`	Incr	32-bit	b00001111
	Seq	`0x0C`			b11110000
		`0x10`			b00001111
		`0x14`			b11110000
		`0x18`			b00001111
`0x0C` (word 3)	Nseq	`0x0C`	Incr	32-bit	b11110000
	Seq	`0x10`			b00001111
		`0x14`			b11110000
		`0x18`			b00001111
		`0x1C`			b11110000

Table 8.90. STM5 to word 4, 5, 6, or 7

Address[4:0]	Operations
`0x10` (word 4)	`STM4` to `0x10` + `STR` to `0x00`
`0x14` (word 5)	`STM3` to `0x14` + `STM2` to `0x00`
`0x18` (word 6)	`STM2` to `0x18` + `STM3` to `0x00`
`0x1C` (word 7)	`STR` to `0x1C` + `STM4` to `0x00`

Table 8.91. STM6 to word 0, 1, or 2

Address[4:0]	HTRANSW	HADDRW	HBURSTW	HSIZEW	HBSTRBW
`0x00` (word 0)	Nseq	`0x00`	Incr	64-bit	b11111111
	Seq	`0x08`			b11111111
	Seq	`0x10`			b11111111
`0x04` (word 1)	Nseq	`0x04`	Incr	32-bit	b11110000
	Seq	`0x08`			b00001111
		`0x0C`			b11110000
		`0x10`			b00001111
		`0x14`			b11110000
		`0x18`			b00001111
`0x08` (word 2)	Nseq	`0x08`	Incr	64-bit	b11111111
	Seq	`0x10`			b11111111
	Seq	`0x18`			b11111111

Table 8.92. STM6 to word 3, 4, 5, 6, or 7

Address[4:0]	Operations
`0x0C` (word 3)	`STM5` to `0x0C` + `STR` to `0x00`
`0x10` (word 4)	`STM4` to `0x10` + `STM2` to `0x00`
`0x14` (word 5)	`STM3` to `0x14` + `STM3` to `0x00`
`0x18` (word 6)	`STM2` to `0x18` + `STM4` to `0x00`
`0x1C` (word 7)	`STR` to `0x1C` + `STM5` to `0x00`

Table 8.93. STM7 to word 0 or 1

Address[4:0]	HTRANSW	HADDRW	HBURSTW	HSIZEW	HBSTRBW
`0x00` (word 0)	Nseq	`0x00`	Incr	32-bit	b00001111
	Seq	`0x04`			b11110000
		`0x08`			b00001111
		`0x0C`			b11110000
		`0x10`			b00001111
		`0x14`			b11110000
		`0x18`			b00001111
`0x04` (word 1)	Nseq	`0x04`	Incr	32-bit	b11110000
	Seq	`0x08`			b00001111
		`0x0C`			b11110000
		`0x10`			b00001111
		`0x14`			b11110000
		`0x18`			b00001111
		`0x1C`			b11110000

Table 8.94. STM7 to word 2, 3, 4, 5, 6, or 7

Address[4:0]	Operations
`0x08` (word 2)	`STM6` to `0x08` + `STR` to `0x00`
`0x0C` (word 3)	`STM5` to `0x0C` + `STM2` to `0x00`
`0x10` (word 4)	`STM4` to `0x10` + `STM3` to `0x00`
`0x14` (word 5)	`STM3` to `0x14` + `STM4` to `0x00`
`0x18` (word 6)	`STM2` to `0x18` + `STM5` to `0x00`
`0x1C` (word 7)	`STR` to `0x1C` + `STM6` to `0x00`

Table 8.95. STM8 to word 0

HTRANSW	HADDRW	HBURSTW	HSIZEW	HBSTRBW
Nseq	`0x00`	Incr4	64-bit	b11111111
Seq	`0x08`
	`0x10`
	`0x18`

Table 8.96. STM8 to word 1, 2, 3, 4, 5, 6, or 7

Address[4:0]	Operations
`0x04` (word 1)	`STM7` to `0x04` + `STR` to `0x00`
`0x08` (word 2)	`STM6` to `0x08` + `STM2` to `0x00`
`0x0C` (word 3)	`STM5` to `0x0C` + `STM3` to `0x00`
`0x10` (word 4)	`STM4` to `0x10` + `STM4` to `0x00`
`0x14` (word 5)	`STM3` to `0x14` + `STM5` to `0x00`
`0x18` (word 6)	`STM2` to `0x18` + `STM6` to `0x00`
`0x1C` (word 7)	`STR` to `0x1C` + `STM7` to `0x00`

Table 8.97. STM9

Address[4:0]	Operations
`0x00` (word 0)	`STM8` to `0x00` + `STR` to `0x00`
`0x04` (word 1)	`STM7` to `0x04` + `STM2` to `0x00`
`0x08` (word 2)	`STM6` to `0x08` + `STM3` to `0x00`
`0x0C` (word 3)	`STM5` to `0x0C` + `STM4` to `0x00`
`0x10` (word 4)	`STM4` to `0x10` + `STM5` to `0x00`
`0x14` (word 5)	`STM3` to `0x14` + `STM6` to `0x00`
`0x18` (word 6)	`STM2` to `0x18` + `STM7` to `0x00`
`0x1C` (word 7)	`STR` to `0x1C` + `STM8` to `0x00`

Table 8.98. STM10

Address[4:0]	Operations
`0x00` (word 0)	`STM8` to `0x00` + `STM2` to `0x00`
`0x04` (word 1)	`STM7` to `0x04` + `STM3` to `0x00`
`0x08` (word 2)	`STM6` to `0x08` + `STM4` to `0x00`
`0x0C` (word 3)	`STM5` to `0x0C` + `STM5` to `0x00`
`0x10` (word 4)	`STM4` to `0x10` + `STM6` to `0x00`
`0x14` (word 5)	`STM3` to `0x14` + `STM7` to `0x00`
`0x18` (word 6)	`STM2` to `0x18` + `STM8` to `0x00`
`0x1C` (word 7)	`STR` to `0x1C` + `STM8` to `0x00` + `STR` to `0x00`

Table 8.99. STM11

Address[4:0]	Operations
`0x00` (word 0)	`STM8` to `0x00` + `STM3` to `0x00`
`0x04` (word 1)	`STM7` to `0x04` + `STM4` to `0x00`
`0x08` (word 2)	`STM6` to `0x08` + `STM5` to `0x00`
`0x0C` (word 3)	`STM5` to `0x0C` + `STM6` to `0x00`
`0x10` (word 4)	`STM4` to `0x10` + `STM7` to `0x00`
`0x14` (word 5)	`STM3` to `0x14` + `STM8` to `0x00`
`0x18` (word 6)	`STM2` to `0x18` + `STM8` to `0x00` + `STR` to `0x00`
`0x1C` (word 7)	`STR` to `0x1C` + `STM8` to `0x00` + `STM2` to `0x00`

Table 8.100. STM12

Address[4:0]	Operations
`0x00` (word 0)	`STM8` to `0x00` + `STM4` to `0x00`
`0x04` (word 1)	`STM7` to `0x04` + `STM5` to `0x00`
`0x08` (word 2)	`STM6` to `0x08` + `STM6` to `0x00`
`0x0C` (word 3)	`STM5` to `0x0C` + `STM7` to `0x00`
`0x10` (word 4)	`STM4` to `0x10` + `STM8` to `0x00`
`0x14` (word 5)	`STM3` to `0x14` + `STM8` to `0x00` + `STR` to `0x00`
`0x18` (word 6)	`STM2` to `0x18` + `STM8` to `0x00` + `STM2` to `0x00`
`0x1C` (word 7)	`STR` to `0x1C` + `STM8` to `0x00` + `STM3` to `0x00`

Table 8.101. STM13

Address[4:0]	Operations
`0x00` (word 0)	`STM8` to `0x00` + `STM5` to `0x00`
`0x04` (word 1)	`STM7` to `0x04` + `STM6` to `0x00`
`0x08` (word 2)	`STM6` to `0x08` + `STM7` to `0x00`
`0x0C` (word 3)	`STM5` to `0x0C` + `STM8` to `0x00`
`0x10` (word 4)	`STM4` to `0x10` + `STM8` to `0x00` + `STR` to `0x00`
`0x14` (word 5)	`STM3` to `0x14` + `STM8` to `0x00` + `STM2` to `0x00`
`0x18` (word 6)	`STM2` to `0x18` + `STM8` to `0x00` + `STM3` to `0x00`
`0x1C` (word 7)	`STR` to `0x1C` + `STM8` to `0x00` + `STM4` to `0x00`

Table 8.102. STM14

Address[4:0]	Operations
`0x00` (word 0)	`STM8` to `0x00` + `STM6` to `0x00`
`0x04` (word 1)	`STM7` to `0x04` + `STM7` to `0x00`
`0x08` (word 2)	`STM6` to `0x08` + `STM8` to `0x00`
`0x0C` (word 3)	`STM5` to `0x0C` + `STM8` to `0x00` + `STR` to `0x00`
`0x10` (word 4)	`STM4` to `0x10` + `STM8` to `0x00` + `STM2` to `0x00`
`0x14` (word 5)	`STM3` to `0x14` + `STM8` to `0x00` + `STM3` to `0x00`
`0x18` (word 6)	`STM2` to `0x18` + `STM8` to `0x00` + `STM4` to `0x00`
`0x1C` (word 7)	`STR` to `0x1C` + `STM8` to `0x00` + `STM5` to `0x00`

Table 8.103. STM15

Address[4:0]	Operations
`0x00` (word 0)	`STM8` to `0x00` + `STM7` to `0x00`
`0x04` (word 1)	`STM7` to `0x04` + `STM8` to `0x00`
`0x08` (word 2)	`STM6` to `0x08` + `STM8` to `0x00` + `STR` to `0x00`
`0x0C` (word 3)	`STM5` to `0x0C` + `STM8` to `0x00` + `STM2` to `0x00`
`0x10` (word 4)	`STM4` to `0x10` + `STM8` to `0x00` + `STM3` to `0x00`
`0x14` (word 5)	`STM3` to `0x14` + `STM8` to `0x00` + `STM4` to `0x00`
`0x18` (word 6)	`STM2` to `0x18` + `STM8` to `0x00` + `STM5` to `0x00`
`0x1C` (word 7)	`STR` to `0x1C` + `STM8` to `0x00` + `STM6` to `0x00`

Table 8.104. STM16

Address[4:0]	Operations
`0x00` (word 0)	`STM8` to `0x00` + `STM8` to `0x00`
`0x04` (word 1)	`STM7` to `0x04` + `STM8` to `0x00` + `STR` to `0x00`
`0x08` (word 2)	`STM6` to `0x08` + `STM8` to `0x00` + `STM2` to `0x00`
`0x0C` (word 3)	`STM5` to `0x0C` + `STM8` to `0x00` + `STM3` to `0x00`
`0x10` (word 4)	`STM4` to `0x10` + `STM8` to `0x00` + `STM4` to `0x00`
`0x14` (word 5)	`STM3` to `0x14` + `STM8` to `0x00` + `STM5` to `0x00`
`0x18` (word 6)	`STM2` to `0x18` + `STM8` to `0x00` + `STM6` to `0x00`
`0x1C` (word 7)	`STR` to `0x1C` + `STM8` to `0x00` + `STM7` to `0x00`

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