ARM1136JF-S™ and ARM1136J-S™ Technical Reference Manual 8.6.2. Half-line write-back

ARM1136JF-S™ and ARM1136J-S™ Technical Reference Manual

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8.6.2. Half-line write-back

The values of HTRANSW, HADDRW, HBURSTW, HSIZEW, and HBSTRBW for half-line write-backs over the Data Write Interface are shown in Table 8.105.

Table 8.105. Half-line write-back

Read address [4:0]	Description	HTRANSW	HADDRW	HBURSTW	HSIZEW	HBSTRBW
`0x00`-`0x07`	Evicted cache line valid and lower half dirty	Nseq	`0x00`	Incr	64-bit	b11111111
	Evicted cache line valid and lower half dirty	Seq	`0x08`
	Evicted cache line valid and upper half dirty	Nseq	`0x10`
	Evicted cache line valid and upper half dirty	Seq	`0x18`
`0x08`-`0x0F`	Evicted cache line valid and lower half dirty	Nseq	`0x08`	Single	64-bit	b11111111
	Evicted cache line valid and lower half dirty	Nseq	`0x00`	Single
	Evicted cache line valid and upper half dirty	Nseq	`0x10`	Incr
	Evicted cache line valid and upper half dirty	Seq	`0x18`	Incr
`0x10`-`0x17`	Evicted cache line valid and lower half dirty	Nseq	`0x00`	Incr	64-bit	b11111111
	Evicted cache line valid and lower half dirty	Seq	`0x08`
	Evicted cache line valid and upper half dirty	Nseq	`0x10`
	Evicted cache line valid and upper half dirty	Seq	`0x18`
`0x18`-`0x1F`	Evicted cache line valid and lower half dirty	Nseq	`0x00`	Incr	64-bit	b11111111
	Evicted cache line valid and lower half dirty	Seq	`0x08`	Incr
	Evicted cache line valid and upper half dirty	Nseq	`0x18`	Single
	Evicted cache line valid and upper half dirty	Nseq	`0x10`	Single

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