The peripheral port clock signal HCLK can run at any frequency, synchronously or asynchronously to the ARM1136JF-S processor clock signal, CLKIN. The ARM1136JF-S processor VIC port can cope with any clocking mode.

nFIQ and nIRQ can be connected to either synchronous or asynchronous sources. Synchronizers are provided internally for the case of asynchronous sources. The INTSYNCEN pin is also provided to enable SoC designers to bypass the synchronizers if required. Similarly, a synchronizer is provided inside the ARM1136JF-S processor for the IRQADDRV signal. If this signal is known to be synchronous, the synchronizer can be bypassed by pulling IRQADDRVSYNCEN HIGH.

These signals enable SoC designers to reduce interrupt latency if it is known that the nFIQ, nIRQ, or IRQADDRV input is always driven by a synchronous source.

When connecting the PL192 VIC to the ARM1136JF-S processor, INTSYNCEN must be tied LOW regardless of the peripheral port clocking mode. This is because the PL192 nVICIRQ and nVICFIQ outputs are completely asynchronous, because there are combinational paths that cross this device through to these outputs. However, IRQADDRVSYNCEN must be set depending on the clocking mode.